This may "yet another" question about decoupling but the question is pretty precise and I can not find an answer.
I have a 40 pin QFN where I need to fan out signals and then place tens of decoupling caps. To make things worse, the IC sits on a socket that occupies 8x the area of the QFN (5mmx5mm). (The socket occupies much area but does not add significant parasitics; it is rated up to 75 GHz). On the same layer I cannot place components within a radius of ~7mm. The backside is restricted as well due to the mounting holes of the socket but at least I can use partial real estate on the back side. But I would need to via down for that. However, I could place 50% of the capacitors onto the thermal ground paddle that I also created underneath the chip on the backside.
Now I have read multiple times there should not be a via between the coupling cap and the pin. But what is worse? Via or longer wire?
In terms of inductance, a 7mm trace would be around 5-7nH (http://chemandy.com/calculators/flat-wire-inductor-calculator.htm). A 22mil diameter/10mil hole is far below 1nH (http://referencedesigner.com/rfcal/cal_13.php).
Best Answer
Don't stress too much its all about minimizing that inductance. That doesn't always translate into distance. If I were you I would take steps to minimize all the contributions to the total path inductance between the pin and the cap. You don't mention what speeds your chip is running at but you do say it's in a QFN. I only say that because sometimes we get obsessed with adding decoupling when the package itself is a limitation.
So how crazy do you want to get? Lets minimize each section. Starting with the caps you could pick a lower inductance package for example a 306 (603 turned sideways), 201s if you can get your values, MLCC caps, or there's an X2Y variant made for decoupling and RF-land.
Next the mounting strategy, if one via is good why not two. More parallel vias should be a lower impedance. If doing 0306, or 201 style caps make sure to do the via to the side trick, again trying to minimize loop area.
Ok so now I say put them on the top. Make part of your top layer a copper flood for the power side. Then on the next layer 5 mil or less below the top make that GND. Use multiple gnd vias at the socket pins. This will give you a nice low impedance path from the above caps into those pins. I did an analysis one time on HS section of an FPGA. A nice tight plane structure and caps like I described outperformed capacitors directly underneath the parts using multiple vias.
Finally if you want to feel better about it you could do some simulation or analysis. There's plenty of topics written about PDN design out there. If you don't have a simulator check out Altera's free PDN excel tool. The design guide has some really nice information in it.
I've used those sockets before they're pretty nice, and have also stressed about where to put caps.