Electronic – Designing a *linear* MOSFET driver stage

The pole formed by the gate resistor and the input capacitance would actually make the circuit less stable. This is because there will already be a pole in the opamp giving a 20db/decade gain change (up to 90 deg phase shift). If you add another pole in the loop you now potentially have 40dB/decade gain change with the phase shift being asymptotic to 180 deg.

I would add a resistor in the connection from the sense resistor to the opamp negative input and then add a capacitor from the output of the opamp to the negative input of the opamp. This can then give you a dominant pole that rolls off the gain before the phase shift in the output stage gives significant phase shift. It cane useful to put resistor in series with the feedback capacitor to give better gain at higher frequencies.

The resistor in the gate of the MOSFET can be useful for stopping high-frequency instability - a value of 22-100 ohms is appropriate there.

This answer does not address how to measure FET \$C_{\text{iss}}\$, because there is no real value in doing that. Since capacitance is such an important FET parameter, the manufacturers provide capacitance data on every datasheet that is definitive in almost every situation. (If you find a datasheet that doesn't provide full data on the capacitance, then don't use that part.) Given the data in the datasheet, trying to measure gate capacitance yourself is a bit like trying to take a picture of Yosemite while Ansel Adams is there to hand you that picture he took.

What is worthwhile is understanding the characteristics of \$C_{\text{iss}}\$, what they mean, and how they are effected by circuit topology.

Facts about \$C_{\text{iss}}\$, that you already know

• \$C_{\text{iss}}\$ = \$C_{\text{gs}}\$ + \$C_{\text{gd}}\$
• \$C_{\text{gs}}\$ is nearly a constant value, mostly independent of operating voltages.
• \$C_{\text{gs}}\$ is not related with and has no involvement with the Miller effect.
• \$C_{\text{gd}}\$ is strongly inversely dependent on \$V_{\text{ds}}\$, and can easily change by an order of magnitude throughout the operating voltage range.
• \$C_{\text{gd}}\$ is the parasitic cause of the Miller effect.

Interpretation of these seemingly simple, but subtle facts can be tricky and confusing.

Wild and Unsubstantiated Claims Regarding \$C_{\text{iss}}\$ -- For the Impatient

The effective value of \$C_{\text{iss}}\$, of how it is manifest, depends on circuit topology, or how and what the FET is connected to.

• When the FET is connected in circuit with impedance in the source, but no impedance in the drain, meaning that the drain is connected to an essentially ideal voltage, \$C_{\text{iss}}\$ is minimized. \$C_{\text{gs}}\$ will virtually disappear, its value being divided by FET transconductance \$g_{\text{fs}}\$. This leaves \$C_{\text{gd}}\$ to dominate the apparent value of \$C_{\text{iss}}\$. Are you skeptical of this claim? Good, but don't worry it will be shown to be true later.

• When the FET is connected in circuit with impedance in the drain, and zero impedance in the source, \$C_{\text{iss}}\$ is maximized. Full value of \$C_{\text{gs}}\$ will be apparent, plus \$C_{\text{gd}}\$ will be multiplied by \$g_{\text{fs}}\$ (and drain impedance). Thus \$C_{\text{gd}}\$ will dominate \$C_{\text{iss}}\$ (again), but this time, depending on the nature of the impedance in the drain circuit, could be unbelievably massive. Hello Miller plateau!

Of course, the second claim describes the most common use case for hard switched FETs, and is what Dave Tweed talks about in his answer. It is such a common use case that manufacturers universally publish Gate Charge charts of it, along with circuits used to test and evaluate it. It ends up being the worst possible maximum case for \$C_{\text{iss}}\$.

The good news here for you is that if you have accurately drawn your schematic, you don't have to worry about the Miller plateau, because you have the case of the first claim with minimal \$C_{\text{iss}}\$.

Some Quantitative Details

Let's derive an equation of \$C_{\text{iss}}\$ for a FET connected as in your circuit. Using a small signal AC model for a MOSFET such as Sze's 6 element model:

^{simulate this circuit – Schematic created using CircuitLab}

Here I've discarded the elements for \$C_{\text{ds}}\$, \$C_{\text{bs}}\$ (bulk capacitance), and \$R_{\text{ds}}\$ (drain to source leakage), because they're not needed here and just complicate things. Find for \$Z_g\$:

\$\frac{V_g}{I_g}\$ = \$\frac{g_{\text{fs}} R_{\text{sense}}+1}{s \left(C_{\text{gd}} \left(g_{\text{fs}} R_{\text{sense}}+1\right)+C_{\text{gs}}\right)}\$ \$\frac{\frac{s C_{\text{gs}} R_{\text{sense}}}{g_{\text{fs}} R_{\text{sense}}+1}+1}{\frac{\text{Cgs} s C_{\text{gd}} R_{\text{sense}}}{C_{\text{gd}} \left(g_{\text{fs}} R_{\text{sense}}+1\right)+C_{\text{gs}}}+1}\$

Now, the second fractional term doesn't do anything until frequency is well above 100 MHz, so we'll just treat it as unity. That will leave the first fractional term, the integrator term, which is the capacitive impedance. Then rearrange to get the effective \$C_{\text{iss}}\$ that matches the topology:

\$C_{\text{iss_eff}}\$ = \$\frac{C_{\text{gd}} \left(g_{\text{fs}} R_{\text{sense}}+1\right)+C_{\text{gs}}}{g_{\text{fs}} R_{\text{sense}}+1}\$ or \$\frac{C_{\text{gs}}}{g_{\text{fs}} R_{\text{sense}}+1}+C_{\text{gd}}\$

Note that here \$C_{\text{gs}}\$ is divided by \$g{\text{fs}}\$ (and \$R_{\text{sense}}\$) , hence obscured by transconductance, and \$C_{\text{gd}}\$ is added unmodified. Also, if \$R_{\text{sense}}\$ = 0, \$C_{\text{iss}}\$ = \$C_{\text{gs}}\$ +\$C_{\text{gd}}\$.

For an IRF530N at \$V_{\text{ds}}\$ = 25V, \$C_{\text{gs}}\$ = 900pF, \$C_{\text{gd}}\$ = 20pF, \$g_{\text{fs}}\$ = 20S: \$C_{\text{iss_eff}}\$ = 63pF. LM358 with 63pF loading ends up with about \$35^{\circ }\$ phase margin ... not oscillatory, but pretty ringy.

But, if \$V_{\text{ds}}\$ where to fall to 3V, \$C_{\text{gd}}\$ would increase to ~200pF (Fig 5 in datasheet), and \$C_{\text{iss_eff}}\$ increase to 243pF. And when using a LM358 OpAmp, with open loop output impedance of ~2kOhms at the crossover frequency, that turns out to be a problem.

Let's look at the response. I'll use a Nichols chart here because that will show open loop and closed loop response simultaneously.

Here, the rectilinear grid is the open loop, while the contour lines show the closed loop (green contours for dB magnitude and gray contours for phase). The blue curve is \$V_{\text{ds}}\$ of 25V, and at the crossover point (at the red dot -- 502kHz), phase margin is indeed \$35^{\circ }\$, and closed loop peaking of about 5dB.

The purple curve is for \$V_{\text{ds}}\$ of 3V, and the corresponding open loop phase margin is ~ \$-3^{\circ }\$. For the closed loop, look at the ascent of mount Nichols, the curve pretty much nails the peak which would ideally correspond to infinite peaking. Of course that won't happen, but the system would be unstable.

It is no surprise that the main problem here is the open loop output impedance of the LM358. Even with a FET-circuit topology that has minimal expression of \$C_{\text{iss_eff}}\$, the LM358 is not adequate. An amplifier with open loop impedance of 50 Ohms or less and phase margin greater than \$75^{\circ }\$ would probably solve the stability problems.