Electronic – Designing a SMPS for low noise

linear-regulatorpower supplyswitch-mode-power-supply

I'm designing a large adjustable bench power supply (up to 250W per channel, 50V max). My current thoughts about the design are three stages:

A unregulated supply at ~60VDC, up to 5A out. Using a mains transformer to generate the 60VDC.

A buck converter that takes me from ~60VDC, up to 5A, to ~1.5V above the requested (adjustable) voltage.

Finally, a linear regulator to take me from the output of the buck converter to the requested voltage.

The linear regulator has to be able to operate at 50V, 5A. Because of this, I'm designing my own. (I'm not aware of any off the shelf solutions).

I know that you can get close to linear regulator noise levels using this topology (unregulated to buck to linear regulator), however you have to pay attention to the noise in your buck regulator and match it with the power supply rejection of your linear regulator.

What are the things that I should pay attention to when designing this system? I know you can reduce the noise in a SMPS by turning on the FETs slower, and that typical linear regulators are better at rejecting low frequencies than higher frequencies. I also know I can use a low pass filter to help filter out the high frequencies of the SMPS, at the cost of ~.5V and some heat.

Are there other things I should take into account? Does synchronous vs. asynchronous matter? Should I design a PI filter after the SMPS to filter out the high noise? Does the op-amp or MOSFET selection of the linear supply change its PSRR frequency response? I would expect the op-amp matters, but the FET less so, what are the figures of merit I should be looking for?

Best Answer

The 60Vdc input from wains transformer is Valid .This means a 60 volt switching waveform and not a 360Vdc switching waveform.Linear post reg is good ,if there are concerns about HF rejection then extra LC filter before the reg is good.The coils and caops for this are not a drama at an average current of 5A .Synchronous will as orthodoxely implemented will be much more noisey at HF .If you still want synch then run the bottom switch in "FIODE " mode .This means that the switching regime makes the fet behave like a diode but with a lower volt drop that is dictated by RDS on .I think that a schottky diode rated at say 100V will be more sensible.Now deal with your turn on by whatever means because turnon into a conducting diode makes lots of HF and VHF noise which is more difficult to filter because capacitors look inductive and inductors look capacitive.I have used a S trap buck for Variable volts off inputs up to 820VDC so 60 wont be a problem . The S trap is a second cousin of a valley switch. Use lots of MLC caps because they are better at HF ripple suppression than ALIMINIUM ELECTROLYTIC CAPS.Sure you need thousands of microfarad on buck input due to 50/60Hz power but your output wont need much electro .Most importantly the ceremics deal with the switchmode ripple .Your design should be doable in SMD.