I just started to learn the sequential logic and I am a little bit confused of the difference between the latch and flipflop. More specifically, I am confused about the difference between edge triggered and level triggered.
So, I learned master slave flip flop first other than other flip flop. Then, I understood pretty well why master slave flip flop is edge triggered. I think it is the NOT gate of the clock signal to the second component that makes it edge triggered.(Not sure whether that second or first component is D flip-flop or D latch either)
However, then I came to learn about this SR flip-flop and even D flip-flop. And suddenly, I got confused about the difference between edge triggered and level triggered.
How is this SR flipflop edge triggered? Shouldn't it be level triggered since as long as the clock signal is HIGH, everytime the input changes, the output will respond to it.
I think flip-flop is always edge-triggered? Am I misunderstanding something?
Best Answer
Indeed you would not be the first person to be confused by the terms edge triggered versus level triggered.
Obviously, something that is level triggered, does trigger at the appropriate edge when the level is first established. Similarly, something that is edge triggered has to reach the appropriate level for the edge to be recognized. So right out of the gate it is confusing.
However, the difference between edge triggered and level triggered actually has to do with the data, not the clock.
A level triggered device will allow whatever changes are occurring on the data pins to propagate through the device until the clock level returns to the non-active state. An edge triggered device the output will change on the appropriate clock edge only.
As you can see from the above, as long as the CK signal is high, you can change the Q outputs with S and R as much as you like.
An edge triggered device, on the other hand, will take a snapshot of the data pin(s) whenever the clock signal transitions from one level to the other, that is, at the edge. After that, assuming hold times are maintained, the data can change as much as it likes, but the output of the latch will still maintain the value when the edge happened.
Internally an edge triggered device is actually a combination of gated level triggered flip-flops.
Note there are three set-reset flip-flops in a D-type latch. The first two are gated by the clock pin. As such when the clock signal goes high, the pre-latched state of the Data is transferred to set or reset the output flip-flop. While the clock is high, the first two flip-flops can not change.
Here is a simulator version to play with.
However, you also need to be aware that there are setup time and hold time constraints involved here. There are race conditions, and metastability issues, that will occur if the clock and data change level at the same time.