I'm putting together an ALU, that I want to synthesize on an FPGA. The carry-look-ahead adder is the one many choose to use as opposed to the ripple-carry adder. However, a thought crossed my mind. The ripple-carry adders I have put together before simply has a series of one bit full-adders connected to each other. My though is, what if I were to design a 4-bit full-adder? I'm not talking about an an adder made up of four one bit full-adders. I'm talking about a single components with 9 inputs (x3,x2,x1,x0,y3,y2,y1,y0,cin). I'm aware this would have 512 possible states (2^(9 inputs)).
What I'm wondering is:
- There is obviously going to be a massive number of gates used, is it worth it?
- If I were implementing all my components using NAND gates with a certain delay or all of this, how much of an improvement in speed would a see in a 32-bit using a.) 4-bit full adders b.) CLA adder c.) 1-bit full adders
- Is there some other implementation of an adder I'm not aware of.
- Although an adder is a very menial part of an ALU, what do most digital designers actual go for? Or do they simply use
assign Sum = X+Y+cin;
Best Answer
To answer #4, at least in code targeted for synthesis, an adder will usually be coded as
assign sum = x + y. This leaves the choice of how to implement the adder up to the synthesis tool. There is a cost/performance tradeoff. Absent tight performance requirements, the tool will implement a ripple carry adder, as that has the lowest cost. If there are more aggressive performance requirements, the tool will implement a more sophisticated structure, at some added cost. Another possibility for FPGA synthesis is that the adder will be mapped to a special-purpose DSP component, if available in the target device.When maximum performance is desired, the logic will be designed by hand rather than implemented with a synthesis tool. In this case, in addition to a high-level reference model with the form
sum = x + y, there would also be a lower-level description describing the individual gates or transistors (this might be done in an HDL, or in a schematic tool). This "maximum performance" scenario would almost certainly be an ASIC implementation rather than an FPGA.To (not really) answer #3, for more than you ever wanted to know about adder architectures, I found this thesis linked from a thread on edaboard: http://www.iis.ee.ethz.ch/~zimmi/publications/adder_arch.pdf.
To answer #1 and #2, the best way to figure things like this out is to do some experiments, anything else is speculation. What you will get for the "4-bit full adder" design depends how you code it. If you code it as an adder, the tool will likely do what it would have done anyways, although it may fail to figure out that the 4-bit adders go together to form a larger adder. If you code it as a logic function, you may get something faster than the ripple-carry implementation, but you may not.