Electronic – Do any devices support handshaking on SPI-ish bus without extra wires


The 4-wire SPI bus has a considerable speed advantage over I²C, but unfortunately so far as I know has no standard way to perform handshaking without using extra wires beyond the four (and four wires is already annoying enough as it is).

For a recent project where the slave was a CPLD, I implemented a nice approach to provide handshaking in one direction (slave can make master wait) and also incidentally eliminate the need for the /FS line. The signals are Clock, MOSI (master-out/slave-in) and MISO (master-in slave-out).

Clock idles low; both MISO and MOSI output on the rising edge of Clock and are sampled on the falling edge. Two or more consecutive rising edges on MOSI wire while Clock is low will reset communication.

When Clock is low and MOSI is high, MISO will indicate whether the slave is ready. When clock and MOSI are both low, MISO will indicate whether the slave wants attention.

While this approach works very nicely when communicating between my CPLD and my controller, it would be nice if the same approach could be used when communicating between two standard microcontrollers. The biggest features that would be necessary to make this work nicely would be:

  1. the ability of the slave controller
    to reset itself upon receiving some
    number (probably 2 or 3) of rising
    edges on MOSI while clock is idle;
  2. the ability of the slave to control
    the clock-idle state of MISO, and
    preferably load separate values for
    use when MOSI is high or when it is
  3. preferably, the ability for the
    master to control the state of MOSI
    that will be output when the clock
    is idle between bytes (in my
    protocol, the commands which need
    handshaking have the LSB set, but
    that's a bit of a nuisance);
  4. for buffered SPI ports, the ability
    for the master to wait on the
    slave's data line.

Do any common controllers or slave devices offer such features, or work in such a way?

Best Answer

"An introduction to asynchronous circuit design" by Davis and Nowick (in particular, Figure 1 and Figure 2 and the nearby text) describes two handshaking protocols as "pervasive". The 4-cycle protocol, aka RZ (return to zero), 4-phase protocol, and level-signaling. And the similar but more complicated to implement 2-cycle protocol, aka transition, 2-phase, or NRZ (non-return to zero) signaling -- which is very similar to the "data strobe encoding" used by SpaceWire and FireWire. Either one sounds like it has most of the features you requested -- it's SPI-like in that there are exactly 4 signals, all 4 signals are one-way (no passive pull-ups), the master can pause the slave indefinitely until it is ready for the next bit from the slave, etc. It also has a feature supercat requested that SPI doesn't have: the slave can pause the master indefinitely until it is ready for the next bit from the master.

I don't know of any chips that have the 4-cycle protocol built in, but it looks like it would be easy to bit-bang on a microcontroller or a CPLD. In fact, it looks like it would be easier to bit-bang than SPI, since (like SPI) the master has no timing requirements, and (unlike SPI) the slave has no timing requirement either.

Is it possible to use the 4-phase protocol for synchronous bit transfers, and somehow build a higher-level protocol on top of that to get the other things supercat wants -- byte alignment, start-of-command frame alignment, attention/busy/idle states, etc?