All CMOS digital integrated circuits I've ever seen connect all the nFET substrates together to GND.
In particular, the IC CMOS NAND gate has one nFET that has its substrate connected to GND, but its source pin connected to some other internal node.
If I build a NAND gate out of discrete nFET and pFET transistors for educational reasons, do I need to duplicate that substrate connection by using a 4-terminal transistor (with the substrate separately pinned out) to get it to work?
Or would that NAND still work just as well with 3-pin discrete transistors, with the substrate "incorrectly" connected to the source pin?
Is there something magic about a 4-terminal transistor that has a "source" pin not tied to its substrate, such as the ones inside an IC, that can't be duplicated by an individual discrete 3-terminal transistor?
(This question was inspired by some coments at Recomendation for a digital inverter made of discrete components ).
Best Answer
The short answer is that you don't need 4 terminal FETs to build CMOS logic.
Some Background:
In a simple CMOS process, (P-type Wafer, N-Wells) the substrate contact is directly connected to the conductive wafer. This means that the body terminal of all NFETs are basically shorted together. A similar effect happens with the PFETs, although it isn't as absolute. They aren't shorted together to improve performance, but because it is cheaper and easier to manufacture.
This brings up a question: If we had to tie the body terminal of all NFET devices together, what voltage would we like it to be? For NFETs, the body-source and body-drain connections normally look like reverse-biased diodes. In order to maintain these diodes reverse-biased, the body voltage must be less than \$V_D \mbox{ or } V_S + 0.6\mbox{ Volts}\$. Typically this is done by tying the substrate/body to the most negative voltage present in the system. In digital systems, this is usually ground \$V_{SS}\$. The body terminal of PFETs is typically tied to the most positive voltage, or \$V_{DD}\$ for similar reasons.
For 3-terminal FETs, where the source and body have been internally shorted, the internal diodes will never be forward-biased if the source is always at a lower voltage than the drain. If you are stuck with 4-terminal transistors building discrete gates, it will work with the bodies connected to \$V_{SS}\$ and \$V_{DD}\$, and it will also work with the body shorted to the source.