Electronic – Does a CPU completely freeze when using a DMA

cpudmamicroprocessorram

I have pretty straightforward question, but I couldn't find an answer to it anywhere.

On a Von-Neumann system where code and data live in the same RAM, the CPU must fetch all its instructions from memory. Now, in order to move large amounts of data between computer components, there is a Direct Memory Access controller that allows peripherals to have access to main system RAM.

My question is this: if the DMA is allowing a (possibly very long) data transfer between, say, the hard disk and RAM, doesn't that mean that the CPU cannot use RAM and therefore can't fetch its next instruction?

In brief, the DMA is meant to replace the processor arbitrating all I/O reads and writes, in order to free up the processor to do other things. However, if it can't fetch its instructions from RAM, then it hasn't been freed up anyway.

Is there some detail that I'm missing here?

Thanks

Best Answer

You are correct that the CPU cannot be accessing the memory during a DMA transfer. However there are two factors which in combination allow apparent parallel memory access by the CPU and the device performing the DMA transfer:

  • The CPU takes multiple clock cycles to execute an instruction. Once it has fetched the instruction, which takes maybe one or two cycles, it can often execute the entire instruction without further memory access (unless it is an instruction which itself access memory, such as a mov instruction with an indirect operand).
  • The device performing the DMA transfer is significantly slower than the CPU speed, so the CPU will not need to halt on every instruction but just occasionally when the DMA device is accessing the memory.

In combination, these two factors mean that the device performing the DMA transfer will have little impact on the CPU speed.

EDIT: Forgot to mention that there's also the factor of CPU cache, which as long as the code that the CPU is executing is in the cache then it won't need to access real memory to fetch instructions, so a DMA transfer is not going to get in the way (although if the instruction needs to access memory then obviously a real memory access will take place - potentially having to wait for a break in the DMA device's use of the memory).