Electronic – Does CPU pipelining always imply a multicycle datapath

cpu

I'm studying the MIPS CPU and I have a very basic question about the datapath. Since the MIPS CPU uses a 5 stage pipeline, that means that the pipeline is using a multicycle datapath, correct? If a CPU has instructions where the Cycles Per Instruction is greater than 1, the CPU is using a multicycle datapath. Correct?

I guess I'm trying to understand if there's ever a case where you can have a pipelined CPU that's NOT using a multicycle datapath. In my mind, pipelining always implies a multicycle datapath. Is that the case? Or are there exceptions?

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A pipelined CPU implies a multi-cycle datapath, precisely because it takes five clock cycles for an instruction to go from Fetch to Writeback.

Where I'm getting confused is here "unlike the multi cycle cpu, the pipelined datapath requires that every instruction use all five stages of execution."

You should finish reading the next paragraph you're quoting. That requirement is just to prevent two instructions from finishing at the same time.

suppose we use the latencies from our multi-cycle cpu, and we try to run a load instruction followed by an add instruction. the load instruction will require five cycles to execute, and the add instruction will require four cycles. so, if we start running the load instruction on cycle 1, it will finish execution on cycle 5. we are pipelining, so we can start running the add instruction on cycle 2, and it will finish on cycle 5. this is a problem: we have two instructions finishing on cycle 5: they will both try to write to the register file on cycle 5. this is a problem, because our register file only has one write port.

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Electronic – Pipeline and real parallelism

Yes. This is the exactly benefit in use a pipeline. The most simple real life example is a laundry.

When you just arrive there, you have dirty clothes that you want to "process". You put the first group of clothes inside the washer and wait until it finishes. When it is ready, you get your first pack of clothes and put all in the dryer machine and fetch and load more clothes into the washer in parallel. When the dryer end its job you then start the "folding cycle", releasing the dryer.

I think you get the idea that while you are folding you can load more clothes in the washer and dry more clothes from the washer in parallel.

The main idea in both cases, processor and laundry, are similar: you can do more in less time by doing parallel jobs.

In the opposite, a processor without a pipeline have to wait all the execution ends to fetch another instruction. Using the laundry analogy again, it is like you only start to wash another group of clothes only after fold all clothes from the first group, wasting time in the middle.

Electronic – Implementing multiplication

At minimum, you need a branching instruction which can determine whether the previous addition generated a carry. Also, performance will be improved enormously if you expand your register set to three or four registers.

Start with one operand in R0 and the other in R1. Start with R2 zero.

Repeat the following sequence eight times (first ADD may be skipped on first pass)

  Add R2,R2
  Add R0,R0
  Bnc Skip
  Add R2,R1
Skip:

Note that if the instruction set includes an add-with-carry instruction, using it for the second instruction would cause this instruction sequence to yield a 16-bit result in R0:R2. Further, if R2 starts non-zero, its value times 256 will be added to the outgoing result.

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Electronic – Pipeline and real parallelism

Electronic – Implementing multiplication

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