pcbpcierouting
It is the first time for me to design a PCB with a PCIe bus. My first design failed, the bus is not working!
Tom helped me in this question and instructed me how to correctly route a high speed bus – thanks!
Ethernet controller not recognized on PCIe bus
I now improved my design, but before spending some more hundred bucks I would like to make sure this should work. Does my routing now look ok? Ground planes and ground vias are not shown.
SPI bus at 50MHz can easily run a couple of inches thru a few vias without hitch. Wavelength of 50MHz is 6 metres but realistically because fast edges are used you need to think ten times faster. Even so that's a wavelength of 60 cm. Rule of thumb is keep tracks smaller than a half of a quarter wavelength (other folk will use other rules of course) and this means 7.5 cm or 3 inches.
Try and keep clock and data same length and if you hit problems on long stretches you might have to terminate at high frequencies with 10pF in series with 100 ohm (more likely on clock than data).
There is no great theory in my answer, just a whiff of theory and some experiences and he odd rule of thumb. Bottom line - use a ground plane - it's no excuse to say you are not familiar with grounding - get familar - it'll be the difference between something always working and something nearly always never working - it's that big a deal.
If I were to suggest how to route this I would propose something more like this:
Best Answer
You'll need to confirm the trace width/spacing requirements to make the differential pairs 100 Ohm. You can use this tool to work out approximate characteristic impedance of various trace width/spacing combinations. I'd suggest 8th width, 8th spacing is a good place to start, though you may need to tune those to match your PCB stackup.
Also, in your routing, the spacing seems to keep changing along the length of the traces which will not maintain constant impedance, you must route the traces with the spacing maintained constant along the length.
Having a look at your layout, I have the following comments.
It's worth noting that for starters PCIe doesn't require any specific phase on the reference clock, nor specific biasing on the P and N side for the clock. That means that you are free to swap the P and N lines of the clock without consequence. If you make that swap, your clock routing becomes much simpler as you no longer need to cross over.
Next a little rearranging of your PCIe Tx/Rx lanes allows for a much cleaner routing. The length of the two pairs doesn't need to be the same, so it doesn't matter if the RX pair is much longer or shorter than the TX pair. That means that if you place your AC caps on the bottom for both TX and RX, you can actually route the TX pair all the way around the RX pair, meaning your vias can be placed directly at the connector.
Finally, liberal use of ground vias (shown in the image as green filled vias) is essential, especially placed symmetrically either side or around wherever the differential traces change layer - the ground vias are needed to allow return currents on the reference planes to swap layers.
Based on that, I'd suggest something like the following - though you will need to route it and check design rules as this was hand drawn in paint.