Trying to makes sense of the following in this LTC1407 datasheet:
It is good practice to drive the LTC1407/LTC1407A CONV input first to
avoid digital noise interference during the sample-to-hold transition
triggered by CONV at the start of conversion.
The same datasheet also has the following note about CONV:
It is best for CONV to rise half a clock before SCK, when running the
clock at rated speed.
So I thought CONV might be driven high at the falling edge of SCK.
But the statement about driving the CONV input first is confusing.
Does it mean CONV shouldn't be driven on the falling or rising edges of SCK and should be offset from those? (see the datasheet's timing diagram)
Looking at interfacing the ADC with Lattice LCMXO2-256 and running the FPGA's clock at the SCK frequency, but then if it needs this offset I would need a PLL (which it doesn't have) or a higher clock frequency to achieve the offset.
Best Answer
Take a snap shot of the timing diagram and mark it up (in red) with what the data sheet tells you in the timing table is my recommendation: -
The above (I believe) answers all your questions.
I would drive CONV on the falling edge of clock-cycle 34 and ensure that at least 1.2 ns elapses before clock-cycle 1 rises (apologies for this correction).