Electronic – Eagle: Pins on FPGA exchangeable, depending on configuration

While I have to agree with the previous answers - you are indeed a lot better off in the long run if you route manually, I feel your question has not really been properly answered.

A quick-and-dirty workaround for you might be

• copy the component(s) to a library of your own
• add a new package, in which you put a GND rectangle around the entire component on the top layer only
• in the circuit, replace the original component with your tampered component
• let the autorouting commence
• go back to your circuit, and swap the component back to its original package.

Now, before the rotten-egg-throwing sets in, a few extra words why you should not do that.

While Eagle takes quite a bit of effort to get the hang of, it is definitely worth practicing these things on simple designs. As you advance, you will get to the point where you have to route manually, because some signals must be laid out in certain ways. There might still be workarounds for each specific problem, but you will never have practiced to place the components in a way that it is possible to route with minimal effort and losses.

Although the lines are routed as differential pairs, it's not necessarily a killer to your kind of application. The amount of crosstalk is actually still likely to be quite small, as diffpairs are often routed closer to the groundplane than to each other. It's not like they are a twisted wire with no shield, where the signals are effectively much better coupled to each other. And the traces are likely to be relatively short I imagine (if you are contemplating parallel transmission).

I would suggest you could happily set up a 25MHz parallel bus, with a series-terminated clock to signal the device at the far end to latch the data. Drive the data on one edge, latch it on the opposite edge, you'll have 20ns of time for crosstalk and reflections to settle out). You could drive the negative side of the clock driver to '0' and place it away from the databus to keep that signal as clean as possible. It doesn't sound that different from how we used to route asynchronous SRAM databusses (all the wires run very close together with an edge triggered write-enable line) and that used to work fine :)