I do have a chip where a pin can have multiple functions depending on the circumstances*.
For clearness I'd like to have multiple pins in my symbol which all map to the same physical pad.
The other way around is easy (use @: GND@1, GND@2, etc.) but when I try to map multiple pins to one pad I find Eagle 6 doesn't let me do that because "It would exceed the number of pads in my package".
*In my example a TI SSL90S901B Ethernet PHY which has bootstrap configuration input pins to configure the chip on reset (with a 2.2k pullup/pulldown) and which are used for other things during operation (eg. LEDs). But this is a common thing. An AtMega88 for example combines SPI and normal GPIO-pins.
EDIT: I tried using wires in the symbol to create fake pins. This would have the benefit of making clear these pins are the same while still allowing multiple usages. However, wires in symbols seem to be completely ornamental in Eagle 🙁
Best Answer
No, you don't want to show multiple connections for the same physical pin on the schematic. This will lead to confusion because anyone else looking at the schematic will expect that each of those connections is actually a different physical pin.
You do this by listing all the possible pin functions in the pin name. For example, here is what my PIC 18F67J60 part looks like in a schematic:
First notice that power pins are at top and ground pins at bottom. That reduces some of the clutter around the remaining pins, and of course makes the schematic more clear on its own. In most cases, a circuit will only make use of one of the functions of each pin. It would be nice if there was a way to highlight the function or functions actually used, but removing the unused functions is worse. It can be quite useful to see what the part could have done or might do with different firmware.
Most of the time how a pin gets used is obvious from the schematic. One trick that greatly helps with this is to show logical direction for pins. I have little arrow symbols in Eagle just for that purpose. They are small and therefore don't get in the way, but help a great deal towards clarifying the circuit. Reasonable net names also help. Here is a small section of a schematic with the direction arrows and net names:
Particularly note the bottom two pins. Those are UART signals to another processor, so thereby are using the TX and RX functions of those pins. Each net can only have a single name, even though it will be the TX function (output) on one processor and the RX function (input) on the other. In this case I named the nets from this processor's point of view. This is the network processor within the overall device, so I named them NETTX and NETRX to help indicate the names are relative to this processor. However, there is potential for confusion at the other processor since NETTX will go into its RX pin and NETRX will go out of its TX pin. The arrows at the other processor will help a lot to head off a likely confusion.