Electronic – Easy resource to learn solving counter problems

You can create a 3-input, 3-output circuit that maps one state in the count sequence to the next. Then feed the 3 Q outputs of the FF's into this combinatorial circuit, and connect the output of the combinatorial circuit to the 3 D inputs of the FF's. Connect all 3 of the FF's clock lines together, and then whenever an active edge comes along the flip flops act like a 3 bit register, and just load up the next value.

While @optronik's answer is one method of doing it, and the one which uses the least amount of hardware, it's not the best approach.

The issue is one of propagation delays. If you use the MSB of counter 1 as a clock for counter 2 what will happen is there will be a delay between the count values.

When the clock signal for counter 1 triggers it to overflow (go from 15 to 0), there will be a small delay between that clock edge and counter 1's output updating. Once the output has updated, counter 2 will be clocked, but again there will be a delay in its output updating. So counter 1 will change its output \$t_p\$ seconds after the clock, but counter 2 won't change until \$2\times t_p\$ seconds after the clock.

This could cause glitches in whatever the counter output is connected too - the problem will become more apparent the more counters you used. This is why we design synchronous counters instead of ripple counters.

There are synchronous solutions to the issue.

1. If your counters are ICs - i.e. not something you have wired up from logic gates - you can make the second counter synchronous with the first by using the same clock for both counters (not the MSB of counter 1).

   a) if the counter has an enable pin, connect the enable of counter 2 the bitwise AND of all bits of counter 1 (i.e. a 4-input AND gate). Connect the clock signal to the clock pin of the counter 2.

   b) If there is no enable pin, you need a 5-input AND gate. Connect four inputs to counter 1 and the fifth goes to the clock signal. The output of the AND gate goes to the clock pin of counter 2. There will be a small propagation delay added, but it won't add up if you cascade more timers.

   I should note that the (b) approach requires a negative-edge clock signal to work correctly. If you have a positive edge triggered flip-flop, you can still use this approach, but instead of a 5-input AND, you need a 5-input OR. The four inputs connect to the negated outputs of counter 1 (i.e. the \$\bar{Q}\$ outputs) and the fifth goes to the clock.

2. If you are wiring up the counters yourself, you can either do the same as in (1), or you can wire up the counter to be and 8-bit counter directly. If you look at your circuit, you should notice that there is a great deal of symmetry between each bit of the counter. Basically you add the same sub-circuit for each bit - so an 8-bit timer would just 8 of the sub-circuits chained together. An n-bit timer, is n of the sub-circuits.