Electronic – Ethernet : mismatch between diff pairs

I'm not sure where you have read that the squiggle design is used for this purpose, i.e. path length matching. From what I can find the only place where a squiggle (like the one you've drawn) is intentionally used in RFID squiggle antennas; and you probably don't want to build one of those on your board!

Below is an example of path length matching from a book I've read (Jacob et al. Memory Systems). There are one or two squiggly looking paths there but only with one or two periods at the most. The pattern shown there seems to prefer a high amplitude of the "squiggle" so that it has a low number of periods/repetitions. Most other routes shown there are lengthened in some way but not by squiggles. The most common lengthening method used there seems to be making pentagonal U-turns (a term I just made up because I don't know an established one) so that an exterior polyline is naturally longer than an interior one. I don't know what software is used to generate those designs (but it's a good question).

After more searching, it seems that a trade term for the squiggles when applied to trace length matching is "serpentine traces".

And I found an article discussing those: A New Slant on Matched-Length Routing by Barry Olney... Well, the article is actually about proposing an alternative to serpentines, but it does have some background before it gets to comparison. It does seem to me however that the very long serpentines shown in that article are for demonstrative/contrast purposes. I've seen at least two dozen network card models up closely in my computing life (in 20+ years) and I cannot remember noticing a pronounced squiggle like yours (or the one in that article) on any of their PCBs... Now it may have existed in the inner layers (on the few boards that had more than two) where it was not visible. Some cards do route their differential signals on the inner layers, as microstrip.

With this serpentine terminology, it turned out they are standard textbook subject. Thierauf's Understanding Signal Integrity book has a couple of pages on this. Alternative terms are (according to that textbook): "meander or trombone traces". If I get this right, the number of periods is to be minimized because each contributes to a ladder-like waveform created by crosstalk between the U-turns, as excerpted below from the aforementioned textbook. This is alas a purely theoretical analysis. .

The book also says that this is only an approximative solution and that a "3D field solver" is needed to fully simulate the real behavior; for example, the signal actually propagates faster in a serpentine than the 2D trace length would indicate. I intuited correctly the recommendation the book was going to draw from that graph; quoting it below:

Because the maximum coupled voltage grows with the number of segments in the serpentine, when laying out a serpentine, it is best to use a fewer number of long segments instead of a greater number of short ones. Fewer segments also mean fewer corners and less uncertainty in the timing and impedance. For these reasons the segments should be long (typically greater than the signal rise time) and few in number. Also, because crosstalk increases as the traces are tightly packed together, laddering can be reduced by increasing the separation between segments.

Finally, the book also mentions placing a grounded guard trace between segments in a serpentine to (further) reduce laddering caused by crosstalk. The book also lists/cites a few more in-depth papers on this serpentine issue:

• Wu, R., and F. Chao, “Laddering Wave in Serpentine Delay Line,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, Vol. 18, No. 4, November 1995, pp. 644–650.
• Rubin, B. J., and B. Singh, “Study of Meander Line Delay in Circuit Boards,” IEEE Transactions on Microwave Theory and Techniques, Vol. 48, No. 9, September 2000, pp. 1452–1460.
• Orhanovic, N., et al., “Characterization of Microstrip Meanders in PCB Interconnects,” Proceedings 50th IEEE Electronic Components and Technology Conference, Las Vegas, NV, May 21–24, 2000, pp. 508–512.
• Shiue, G., et al., “Improvements of Time-Domain Transmission Waveform in Serpentine Delay Line with Guard Traces,” IEEE International Symposium on Electromagnetic Compatibility, EMC 2007, Honolulu, HI, July 9–13, 2007, pp. 1–5.
• Nara, S., and K. Koshiji, “Study on Delay Time Characteristics of Multilayered Hyper- Shielded Meander Line,” IEEE International Symposium on Electromagnetic Compatibility, EMC 2006, Vol. 3, Portland, OR, August 14–18, 2006, pp. 760–763.

On a more practical note, NXP has an app note DisplayPort PCB layout guidelines (AN10798) that touches on several aspects of trace lenght mathcing on pp. 4-6. They recommend the serpentine design shown below, which also obeys other rules, like not allowing too much distance between differential pairs.

Things that spring to mind:

• usually, you'd model your PCB trace as transmission line that has exactly the same characteristics on the top, as on the bottom layer. As such, it doesn't make much of a difference where on the length of a trace you put the via; so instead of having these "looking like boobies" vias right next to each other, I'd just offset them enough to keep them in the middle of your trace
• R51, C5 could as well be on Top Layer
• I don't know the frequencies of your xtal or CPU, but chances are that the 125 Mbaud of Gigabit ethernet won't be much impressed :) however, if you're nervous about coupling, you might want to consider the classical star-like multiple ground-plane architecture. I don't think this'll be necessary here – Gigabit Ethernet Network PHYs aren't exactly bleeding edge in 2016, so even with some interference, they should work.
• just looking at the part of the layout I see, I'd say it might be easier to route if you just rotated the PHY by 90° – but that might break down the moment the complexity on the "processor side" of the phy comes into play.
• I think your RJ45-magnetics layout is OK; I'd probably been lazy and just routed the two diff pairs that are at the right half of the transformer "down" from the connector's pins, and the left half "up"; but that wouldn't have saved you from the one pair that crosses the other if you're supposed to access the magnetic's pads only from one side (unless you fit two traces between adjacent RJ45 pins...) . Topology is not always your friend :/

Notice: 1GE has a baudrate of 125 MBaud, i.e. even if considering the first two sidelobes, you really shouldn't be worried about frequencies above 375 MHz. With FR4 (with specific epsilon), and a lot of laziness approaching formulas, the wavelength of that frequency is roughly \$\frac15 \frac{c_0}{375\text{ MHz}}= \frac 15 \frac {3\cdot 10^8 \frac{\text m}{\text s}}{3.75 \cdot 10^8\frac1{\text s}}\approx \frac4{15}\approx 0.27\text{ m}=270\text{ mm}\$, so a 2mm trace length difference is but 2.7° phase error ... I think you'll be fine, even with a bit of unelegant routing.