Point 1 and point 2 are quite accurate I would say. For point 3, I always search for the following graph when I'm looking for the likely conduction capabilities of FETs: -

It tells me that if I put 3.5V on the gate and I want to pass 10A drain current there is likely to be 0.5V dropped across the device leading to a power dissipation of 5W. This is an on-resistance of 50 m\$\Omega\$. However, if i used a gate drive of 10V, I can expect the voltage dropped by the device to be about 0.25V i.e. a power dissipation of 2.5W or an on-resistance of 25 m\$\Omega\$.
Regarding the state of "fully-on" you can see that there is no magic state that is reached at some arbitrary gate voltage but I'd say that at about 4.5V gate drive, the benefits of driving with a higher gate voltage are diminishing.
Figure 3 in the data sheet (which shows the graph which you deduced the on resistance variation of 10 m\$\Omega\$) is a derivation of the graph (figure 1) in my answer. Obviously, Figure 1 carries more information because it covers a wider range of gate voltages.
Looking into the drain, the small-signal resistance is $$r_{id} = r_o = \frac{\lambda^{-1}+V_{DS}}{I_D}$$ if the source is at AC common (common-source configuration).
If the AC resistance from source to common is \$R_{ts} \ne 0\$, the small-signal resistance looking into the drain is
$$r_{id} = r_o \left(1 + \frac{R_{ts}}{r_s} \right) + R_{ts}$$
where
$$r_s = \frac{1}{g_m}$$
Looking into the source, the small-signal resistance is
$$r_{is} = r_s$$
The above assumes the body is connected to the source.
I understand why r02 is in parallel with Rf, but what is the 1/gm2
resistor doing there?
The lower right circuit is drawn oddly and further, seems to mix AC and DC sources which is an error.
If I were teaching this circuit, I would draw the AC circuit, with Q1 and Q2 replaced by their small-signal T-models, as follows

simulate this circuit – Schematic created using CircuitLab
Now, is it clear why \$r_{s2} = \frac{1}{g_{m2}}\$ is there?
Edit: on second thought, I don't understand also why the first r0 is
at the drain of the first transistor, and the second r0 is at the
source of the second transistor.
\$r_o\$ connects to the drain and source.
Since, for Q1, the source is grounded, \$r_{o1}\$ connects from D1 to ground.
Since, for Q2, the drain is AC grounded, \$r_{o2}\$ connects from S2 to AC ground.
Best Answer
Vgs is just the voltage from gate to source (with the red lead of the multimeter on the gate and the black one on the source). Everything else is from context.
The Absolute Maximum Vgs is the maximum voltage you should ever subject the MOSFET to under any conditions (stay well away). Usually the actual breakdown is quite a bit different (borrowing from this datasheet):
Vgs(th) is the voltage at which the MOSFET will 'turn on' to some degree (usually not very well turned on). For example, it might be 2V minimum and 4V maximum for a drain current of 0.25mA at Tj = 25°C (the die itself is at 25°C).. That means that if you want your 20A MOSFET to really turn on fully (not just conducting 250uA) you need a lot more voltage than 4V to be sure about it, but if your Vgs is well under about 2V you can be pretty sure it's well turned off (at least around room temperature).
Rds(on) is always measured at a specified Vgs. For example, it might be 77m\$\Omega\$ with Vgs = 10V and Id = 17A and Tj = 25°C. That 10V is the Vgs you need to feed your MOSFET for it to be happily turned on so it looks like a very low resistance.
Vgs also comes up when you want to know the gate leakage. Igss might be +/-100nA at Vgs = +/-20V and Tj = 25°C.