A delta-sigma modulator, used in both ADCs and DACs, comprises a difference (delta) circuit that measures the error between the input signal and the feedback signal, followed by an integrator (sigma), a quantizer (often just a comparator that yields one bit of information) and a time-domain sampler. The output of the sampler is fed back to the difference circuit through a suitable inverse quantizer (i.e., 1-bit DAC).
The trick to understanding noise shaping is to consider the quantizer as linear summing circuit that adds a "quantization noise" signal to the output of the integrator. You can then use superposition to separately evaluate the effect of the circuit on both the original signal and the quantization noise "signal".
For the original signal, the integrator is in the feed-forward path, and as you might expect, it acts as a low-pass filter for that signal — high frequencies have lower gain than low frequencies.
However, for the quantization noise signal, the integrator is in the feedback path, which means that overall, the circuit functions as a high-pass filter for the noise, reducing its gain in the low frequencies (where the desired signal is) and increasing it at the higher frequencies, where it will be subsequently removed by another filter.
It is this noise shaping that accounts for the reduction in noise density in the final passband.
Such products definitely exist, but it will be difficult for you to find a product which will fit into your project requirements precisely. For an audio frequency digital filters you can check out QuickFilterTech. For higher radio frequencies (>1GHz) Hittite comes to mind.
However, if you need to operate in the smaller 10s of MHz range, you will probably have to do what most people do: get yourself a smallish DSP or FPGA and use vendor supplied tools to generate a filter firmware (all major vendors have those; parametric design with GUI wizards and pictures supported).
In fact, the best (and most often used) contemporary approach for a single chip embedded design may be just this: FPGA implementing both the MCU and digital filter in the same firmware.
Update
Just noticed that you've already got a Spartan FPGA in your project. You can use Xilinx FIR compiler to generate a fixed filter out of the box (and use frequency shifter to do the tuning) or you can research some of the approaches for tunable filter implementation in the FPGA (some are not very difficult, plenty of publications around).
Best Answer
I guess it depends on several factors, among others the order of the filter, but you have a few possibilities:
We use a variation of alternative 3 in some of our test setups, not because we cannot generate the slow waveforms required, but because the <0.01Hz cutoff of our analog filters would take way too long to characterize if we tried even a rough frequency sweep. This reduced the testing time from more than an hour to mere minutes.