Electronic – FET – Source follower utilizing current source to lower voltage offset

current-sourcefettransistors

I understand that if I use a FET as a source follower, the signal will be slightly attenuated due to the fact that there is some small inherent resistance in the FET, creating a voltage divider effect between the FET's internal resistance and the source resistor Rs.

In the student manual for 'The Art of Electronics' (Horowitz), he shows a diagram that implies using a current source in the place of Rs can create a circuit with no attenuation. As is the case with many diagrams in this book, his explanations kind of glaze over what is going on, without going into great detail.

In this particular situation, he's aiming to have 2 mA Id current flow. He picked the 1.4k resistor from the curve of ∆Id vs ∆Vgs given this current requirement – making Vgs = -2.8V.

In the diagram, he traces his reasoning: (1) Here drops Vgs, (2) so same current also drops Vgs here … so Vout = Vin.

I get why Vgs drops across these resistors, but I don't understand how he arrives at the conclusion that Vout = Vin. In particular, I don't see why the voltage at the source of the top FET should be equal to Vin+Vgs.

Can anyone shed some light on this confusion?

Here's the diagram:

enter image description here

Best Answer

First, \$v_{in}\$ is an AC signal voltage while \$V_{GS}\$ is a DC bias voltage. These are treated separately.

From a small-signal perspective, the current source (lower FET) is effectively an open circuit so there is effectively no voltage division for the AC signal. This is why \$v_{in}\$ appears at the output node unattenuated (assuming the output node is connected to an effectively open circuit).

From a DC bias perspective, the gate of the top FET is at (presumably) zero volts so the source, which must be more positive than the gate, must be at 2.8V (using the values in the book and assuming the FETs are identical).

However, note that this is not \$V_{GS}\$ since, in fact, \$V_{GS}\$ for both FETs is -2.8V. In other words, the voltage at the source of the top FET is $$v_{in} - V_{GS}$$