Electronic – flash memory wait states

flashmemoryprocessor

I'm using a freescale PowerPC microcontroller. In the flash memory module in the datasheet, the number of "wait states of the flash memory access" is configurable.

The following is the part of the datasheet raised my question, it's taken from the register description of the PFlash module registers :

This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash. Higher operating frequencies require non-zero settings for
this field for proper Flash operation.
0 MHz, < 23 MHz, wait states required = 0 —
23 MHz, < 45 MHz, wait states required = 1 —
45 MHz, < 68 MHz, wait states required = 2 —
68 MHz, < 90 MHz, wait states required = 3 —

(PFlash is Platform Flash controller module)

I understand that the processor is faster than the flash, that's why wait states are introduced. What I don't understand, is : if processor is faster than flash, then the processor is the one that needs to be slowed down not the flash, but the paragraph above says the opposite (or did I not understand this?), it says that in case the Pflash is operated with high frequencies, then we need to slow it down by adding to it additional wait states !!

What's wrong with my understanding ?

Thanks

Best Answer

To amplify stevenvh's answer, any type of logic, when given an input signal, will take some time to produce an output signal; memory is often very slow compared with other logic. Often, there will be a guarantee that the output signal will become valid within a certain amount of time, but that's it. In particular, it's possible that the signal might change several times within that interval, and there will be no indication, prior to the end of that interval, that the signal has achieved its final "correct" value.

When a typical microcontroller or microprocessor reads a byte (or word, or whatever unit) of memory, it generates an address and, some time later, looks at the value output by the memory and acts upon it. Between the time the controller generates the address and the time it looks at the value from memory, it doesn't care when or whether the output signals from the memory change. On the other hand, if the signal from memory hasn't stabilized to its final value by the time the controller looks at it, the controller will misread the memory as having held whatever value was being output at the moment it looked. Normally the controller would look at the value from memory as soon as it was ready to do something with it, but if the memory's value wouldn't be ready then, that might not work. Consequently, many controllers have an option to wait a bit longer after they're ready to process data from memory, to ensure that the output from memory is actually valid. Note that adding such delay will slow things down (the controller would have been happy to act on the data from memory sooner), but will not affect correctness of operation (unless things are slowed down so much that other timing obligations cannot be met).