Electronic – Flip flop counters

Think of your special counter as a state machine. Then assign the state the coded value of the count sequence that you want. In this case the states would be as following with the next state showing.

State    Next State
  3  ->   1
  1  ->   4
  4  ->   7
  7  ->   2
  2  ->   3

Each state can be encoded into three binary bits so your design will require three D type flipflops. You need to make up a set of three karnough maps, one for each flipflop that, shows the next bit value for the flop flop (D input) based upon the three current state (Q outputs).

Use the k-maps to simplify the logic down to the minimal required. Finally you can code the minimal logic up in a series of AND gates driving OR gates into each FF D-input.

Here I show the k-map for the lowest ordered bit of the "counter" to get you started with the idea.

The only change that is required to convert your falling-edge triggered flip-flop to a rising-edge triggered flip-flop is to swap the true (non-inverted) clock and the inverted clock at the pins of your tri-state buffers and the transmission gate. For example, the center transmission gate in a rising-edge triggered flip-flop would have the true clock connected to the NMOS transistor and the inverted clock connected to the PMOS transistor.

By the way, near the middle left of your diagram you have a circled inverter that shows Q at its output and !Q at its input. That's correct...the output of the inverter just to the right of the circled inverter is !Q (Q-bar) rather than Q. If you follow the path from the D input through an inverting tristate buffer and the NOR gate you will see that the signal at the right end of the (non-inverting) transmission gate must have the same polarity as D, so that point in your circuit represents the true (non-inverted) Q value.