Electronic – Flip flop with load/set, reset, clk, and input

digital-logicflipflopresetverilog

I'm not looking for a hardware language description of the flip flop, but the logic gate level to implement.

In verilog, the equivalent I'm looking for is

always@(posedge clk or negedge reset)
begin
    if(~reset)
      Q <= 1'b0;
    else if(~load)
      Q <= D;
    end

I've looked at: http://reviseomatic.org/help/e-flip-flop/4013%20D-Type%20Flip%20Flop.php
and
http://www.csee.umbc.edu/~squire/images/dff.jpg

the problem with the above implementation is that after I set a value to Q (D=0,Q=0,load=0) with load(set in picture) = 0, then when i set load high load = 1 on the next clk cycle, i get (D=x,Q=1,load=1). In order words, changing load from true to false will change the value of Q, but I want Q to hold it's previous value.

What is a flip flop that would hold it's value on Q after it has been set and enable is set high?

Best Answer

You've been looking at incorrect components: D type flip-flop is used to sample the D input on each clock cycle, but you want to use load signal in order to enable sampling. Please note that the signal set which you wanted to use as load has different funtionality - it causes the output to go high (regardless of the value of D).

What you are looking for is D Flip-Flop with Enable. There are two simple approaches to add this functionality to a regular D-FF.

Feedback:

Adding a MUX which is controlled by Enable signal. On each clock edge the flop will either sample the new value, or the old value (which is equivalent to keeping an old value).

enter image description here

Clock gating:

Instead of MUXing the input to the flip-flop, you may simply disable the clock when you do not want to sample a new value. This approach is widely employed in order to reduce the power consumption (no clock -> no activity -> no active power consumed).

As pointed out by @Supercat in the comments, clock gating is the more sophisticated technique which requires a bit more expertise because it presents additional delays in clock path.

enter image description here

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