Electronic – FPGA: count up or count down

fpgapapiliovhdlxilinx

I am learning to use an FPGA (Papilio development board,which has a xilinx spartan3e, using vhdl).

I need to divide an incoming pulse by a (hard coded) number.

I can see 3 options – roughly, as pseudocode (using 10 counts as an example):

  1. Initialize to 0, on input rising edge increase by 1, compare to 10; if they are equal, reset to 0 and trigger output pulse
  2. Initialize to 10, on input rising edge decrease by 1, compare to 0; if they are equal, reset to 10 and trigger output pulse
  3. Initialize to 9, but make sure there is at least 1 leading "0" bit, which is my output bit. On input rising edge decrease by 1. On rising edge of the output bit, reset.

The duty cycle is unimportant.

Is one of these better than the others? Is there an even better method that I haven't thought of?

Is there a "standard" way that will give the compiler the best chance of optimizing?

Best Answer

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your control, including the fitter's random number seed.

Having said that, I believe that option 3 will be the best. Options 1 and 2 have a comparator/OR gate going between the counters so that it can signal that the target number has been reached. Option 2 may be slightly faster than 1, since it all can be straight OR'd together without any inverters, but again you run into small technology differences where it may be faster to AND or XOR.

Option 3 skips the comparison for the low cost of one extra bit in the counter. This should be worth it, unless you are severely restricted in flip-flops.

One fun fact about counters is that they tend to be grouped into a device specific size within a logic block, and you will see the timing change more than expected if this extra bit pushes you out of that group.