Electronic – generate random numbers using LFSR

verilog

I have to generate 2 5-bit random numbers and add them using structural verilog and implement it on FPGA. I have to design LFSR with 5 D flip flops and the 5-bit pseudo random number is given by the outputs of the flip-flops. The 5 flip-flops are connected in serial and the 5th flip-flop is xor-ed with the first.

This is the code I have written so far. I am new to verilog and electrical concepts.

module dff (Q, D, Clock);
 output Q;
 input D;
 input reset;
 input Clock;

 reg Q;

 always @(posedge Clock)
 begin
   if (reset)
     Q = 1;
   else 
     Q = D;
 end
endmodule

module DFF_LFSR() ; 
 input D;
 input clk;
 input reset;
 output Q1, Q2, Q3, Q4, Q5;
 reg Q; 

 dff DFF1(Q1^Q5, D, reset, clk);
 dff DFF2(Q2, Q1, reset, clk);
 dff DFF3(Q3, Q2, reset, clk);
 dff DFF4(Q4, Q3, reset, clk);
 dff DFF5(Q5, Q4, reset, clk);
endmodule

Best Answer

Regarding the general idea of use LFSRs to generate pseudo-random numbers:

As a digital designer, I can say that it's rather common to see LFSRs used to generate "low quality" random numbers. It's a perfectly acceptable approach for many designs.

The biggest problem I see with your fundamental approach is that you want a 5-bit random number, but you're just using a 5-bit LFSR. That design will produce values which are no more random than a counter that counts from 1-31 and repeats--you'll never see the same value twice without first seeing all the other possible values.

The better approach would be to create an LFSR that is much wider than 5 bits, and just take the low 5 bits as your "random" value.

On a side note, Xilinx has an App Note which includes list of taps for various widths of LFSR counters from 3 to 168 bits.

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Difference between blocking and nonblocking assignment Verilog

was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel.

Blocking assignment executes "in series" because a blocking assignment blocks execution of the next statement until it completes. Therefore the results of the next statement may depend on the first one being completed.

Non-blocking assignment executes in parallel because it describes assignments that all occur at the same time. The result of a statement on the 2nd line will not depend on the results of the statement on the 1st line. Instead, the 2nd line will execute as if the 1st line had not happened yet.

Electronic – the set in D FF

The Set-Reset-flip-flop is not often used, the syntax tends to look 'wrong' to those not used to seeing it. You can actually have 3 edge sensitive signals in the sensitivity list: Active low reset has priority.

always @(posedge clk or negedge reset or posedge set ) begin
  if (~reset) begin
    Q<=1'b0;  
  end
  else if (set) begin
    Q<=1'b1;  
  end
  else begin
    Q <= D;
  end
end

For a counter which will increment by 1 when enabled, there is no d=need for set_reset_flip-flops.

A clean RTL version could just be:

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
   Q <= 'b0;
  end
  else begin
    if (increment) begin
      Q <= Q + 1'b1;
    end
  end
end

Where increment is a synchronous signal. This has 3 flip-flops Q feeding into a Half adder with a single bit 1 as the other operand. You only need a half adder to increment by 1.

Best Answer

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Difference between blocking and nonblocking assignment Verilog

Electronic – the set in D FF

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