Electronic – GPIO push/pull and pull-up resistor

gpiopicpulluppush-pull

I have a question regarding the behaviour of a MCU's GPIO pins when configured in a certain way in hardware and software. In this case I am using a dsPIC33EP, but I believe this question is generally applicable to MCUs with push/pull outputs. At certain points in the circuit I am developing I need a pull-up resistor on the line to ensure that the connected chip has a hardware default state (in this case HIGH) even when the PIC has been turned OFF. If I pull up this line to a voltage equal to or greater than the power supply of the PIC (3.3V) but the PIC outputs a HIGH at slightly-below whatever this voltage level is… what happens to the output of the PIC?

I am using a 5V-tolerant pin on the PIC, which in the electrical specifications guarantees that it will tolerate up to 3.6V when the PIC is off, so that is not an issue. What I am uncertain about is how the PIC handles a (small) over-voltage condition on an output through a pull-up resistor.

If Vp is greater than VOH, will there be damage done to the chip?

GPIO Setup

On a side note, I have considered some solutions to this problem and will likely set up these outputs in software to behave as open-drain types. My question is regarding the feasibility of doing it using PUSH-PULL outputs, but if anyone has any other simple solutions to offer for application's sake, please feel free!

Best Answer

What your solution will do when the PIC is powered down depends on the pin type (some are 5V tolerant which means there is no diode to the power rail).

Looking at the absolute maximum ratings for 5V tolerant pins shows a maximum of 3.6V when Vdd < 3.0. Whether this holds true when powered off is not specifically answered, but as it appears to be an electrostatic stress rating, I would suspect so.

For normal operation, the output voltage depends on load as you will see in the output driver specifications. Although the minimum output voltage that is guaranteed is 2.4V, the more likely output voltage will be far closer to Vdd for an interface to a high impedance input.

I notice that you pull up to 3.4V - is that because your module has true CMOS inputs? (transitions at 1/3 and 2/3 Vdd).

Edit: The dsPIC33EP absolute maximum rating for Vdd > 3.0V on a 5V tolerant pin is 5.5V, so I don't really see an issue if you don't exceed that.

Some current will flow into the line if the pullup exceeds Vout, so the the PIC output is high but lower than the pullup, then the pullup will tend to try and backfeed the pushpull output. Provided you do not turn on the body diode of the upper FET (a diode drop), I would not be particularly concerned.