Assume the positions of everything are fixed. Let's also assume a 4-layer board for simplicity. The outer layers are signal layers, and the inner layers are two planes for Power and GND.
As can be seen from the image, there is a large hole in the middle of the board. The board will transmit data at 16 MHz (wavelength ~18m) from the ADC to the "Master" board via a connector.
Is there any concern that digital signals leaving the ADC will return to the connector in both clockwise and counter-clockwise paths?
Would it be better to break the plane such that this cannot occur?
Some quick LTSpice with arbitrary simulation parameters seems to suggest that NOT breaking the loop is the way to go. As seen below, leaving the loop decreases the return's inductance since the two paths are essentially in parallel: