Electronic – Half Bridge with PWM- gate signal problem

Start here to get a general idea - Many many ideas here

Leading to

http://forums.parallax.com/showthread.php/130577-PWM-phase-sync

The high:low ratio of the PWM over 1 PWM cycle sets the analog value represented after filtering. The PWM ratio is adjusted accordingly. But how to do so ...

Here's how:

The comparator compares linear ramp & sine wave magnitudes - and toggles the output according to the result.

And the next one is like unto it ...

I expect you to now run from the room crying "Eureka".

YeeHa!!!

This

Yee Ha !!!

From Here

Makes this:

Notes:

Note that one diagram above uses a triangle wave and the other a sawtooth (ramp up, vertical down). Look at what they both do and how the method works. Once you understand what is being done you can "easily enough" convert it into software. The "ramp" in both cases starts at zero and progresses to Vmax over a period of time. With an analog comparator you continually compare the sine wave with the ramp and set the output high when the ramp is lower than the sinewave and low when the ramp is higher. In software the comparison is done at regular time steps

The overall ramp frequency needs to be higher than the sine wave frequency. The more ramps per sinewave cycle the more often the waveform will switch and the higher the PWM frequency and the more losses in MOSFETS or IGBTs etc. But, lower ramps per sinewave lead to a worse approximation of the sine wav when the PWM is filtered. Some systems change the number of samples per sinewave depending on the frequency to limit maximum PWM rate. As sinewave frequency gets higher they will occasionally reduce the ratio. When such systems drive a motor you can hear them "gear changing" a the motor accelerates. Starter from stationary the inverter PWM can be heard as a low frequency tone which rise towards a whistle as the motor speed rises, then suddenly drops by a factor of maybe 4 or 8 or ... and then rises again as the motor continue to accelerate. It may do this several times. This allows the purest possible sine wave at slow speeds and limits drive frequency components at high speeds.

Note that you need model this for only a quarter cycle in software. For the second quadrant you just run the comparison backwards to quadrant one, for Q3 you invert Q1 (highs and lows swapped) and for Q4 you invert Q2. The sinewave values may be calculated on the fly or stored in a table depending on what suits your system. If you have lots of ROM/memory room it may be easier to use a whole 360 degrees in memory but using 1/4 cycle 4 times is not much harder.
So, if using a table:

Q1 - Up table
Q2 - Down table
Q3 - Up table, output inverted
Q4 - Down table output inverted.

Which reminds me of an old old joke*.

What can go: Up a chimney down and Down a chimney down
but cannot go Down a chimney up or Up a Chimney up ?

(In some case, trying to go up a chimney up may work after a fashion if you try hard enough but may lead to disaster but down a chimney up always ends in disaster. )

When it is charging (input to the transistor low), it is charging towards 10V through a resistance of 6.45K ohms (the Thevenin equivalent source resistance of the divider plus the 4.7K resistor), and when it is discharging (input to the transistor high) it is discharging through a resistance of 4.7K ohms (to maybe 50mV- the VCE of the saturated transistor- it won't make much difference so I'll guess at it- you can refer to the datasheet for a slightly better value).

For steady state, assume the voltage is fixed (does not change during a cycle), so we know the current charging must equal the current discharging if the times are equal (ask if that is not obvious).

So (10 - Vc)/6.45 = (Vc - 0.05)/4.7

solving, Vc = 4.244V. (Even worse!)

I don't know where the value in your simulation comes from but there will be lot of ripple in the voltage with such a small capacitor. Figure about 0.001 second * 0.9mA/10^-6 = 0.9V, so +/-450mV ripple (about 10%), so perhaps it's the peak voltage, not the mean-> 4.244 + 0.45 = 4.694, which agrees with your simulation.

You can use a more symmetrical drive either by increasing the 4.7K to a much higher value or using a CMOS buffer that will also get rid of the Vce(sat) term. Just remember that the buffer does not make this issue magically go away, and if you have a relatively low resistance compared to the buffer output impedance, and that impedance is asymmetrical (as it usually is) you may not see the exact voltage you're expecting.

Note that using a highly asymmetric switch like this one introduces a significant nonlinearity, which may be undesirable. In this case, it's about -15% of signal at mid-scale or -7.6% of full scale.