Electronic – hardware implementation of division algorithm

algorithmarithmetic-divisioncomputersdigital-logic

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I have tried hard but I don't understand how this algorithm is working.Please explain the flow chart.

\$DVF\$ is the divide overflow flip flop.

\$A_s\$ is the sign bit of \$A\$

\$B_s\$ is the sign bit of \$B\$

\$E\$ is the register that has a carry bit

Initially the XOR operation is carried out to check if the sign bits of two numbers is equal.

The dividend is \$A\$ and \$Q\$ and the divisor in \$B\$.
The sign of the result is transferred into \$Q_s\$ to be part of quotient. \$SC\$ is the sequence counter.

I am unable to understand the sequence of operations . What happens after the carry bit is checked for 1 or 0 ?

Best Answer

Flowcharts are often not a very precise way of indicating what hardware is doing, since flowcharts often imply the existence of a single execution process, whereas hardware often does many overlapping and simultaneous operations.

The portions of the diagram circled in red seem a bit odd. It seems odd to latch A with the value after subtracting B, and then re-add B. More natural would simply be to not bother latching the lower part of the subtraction result. I think the flowchart might be clearer if "named values" were separated into "registers" and "values", and each step either computed values or registers. Thus, for example, one could have something like (assuming 16-bit registers)

C:T[15..0] = (A[14..0]:Q[15]) + ~B-1
if (C or A[15])
  A[15..0] = (A[14..0]:Q[15])
  Q[15..1] = Q[14..0]
  Q[0] = 1
Else
  A[15..0] = T[15..0]
  Q[15..1] = Q[14..0]
  Q[0] = 0
Endif

Every step that updates registers would represent a system clock. Events that merely compute values would not require a clock edge, but would be processed asynchronously.

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