Electronic – High side P channel MOSFET power switch – gate question, and suggestions for the circuit

interfacemosfetpower electronicsswitches

My circuit is for switching a 12V battery to a load (LED lights, designed for automotive use), during my testing with prototypes, the lights consumed about 400mA, meaning they were ~5W LED products.

12V 0.5A high side PFET power switch circuit

I would like some feedback on the way I've done the pull up/pull down control interface for the P MOSFET with additional LED indicator.

First, I shall describe the labels and components briefly:
BATT_ON is the 12V power connection to battery, through a automotive blade fuse and a switch (which I just realized will have to be changed so it's not a series switch.. rather for current handling reasons be another PFET pass element arrrgh..)

OUTPUT2B is my digital output from 3.3V microcontroller.

OUTPUT4 is the high power load output. The load's return is connected to the Battery negative terminal through the system's common ground. This is a standard high side only switch (the load's ground is not floating).

R1 is a pull-up resistor in normal conditions (PFET being off) and acts as a current limiting resistor for the small onboard 0603 sized LED "OP1"

OP1 small 0603 sized SMD LED used for indication that the PMOS is output is "ON"

R8 is a pull down resistor to ensure no floating pin/noise can accidentally turn on Q3A

R7 is the base current limiting resistor.

Q3 (A because it's part of a dual NPN package) is the BJT that pulls down the P Channel MOSFET's Gate to turn it on.

Q1 the P channel MOSFET switch. A little SOT23 package whose part number and ratings are shown in the picture text.

My main question is:

When OUTPUT2B is ON, and Q3 is turned on, Q1's gate will be discharged to allow the FET to turn on – but while R1 is supplying current to the LED (OP1), will it also create issues with the gate of Q1? How can I quantify this, if it will be an issue? Will there be charge contention at the gate, leading to undesired behaviour in the Source->Drain?

Normally I would just pull the gate straight to ground in this 3.3V->12V high side switch interface, and i've done this before with no issues. In a prototype with very limited testing (and I do not have access to it anymore) I did actually implement this but never got the chance to analyse the gate behaviour.

Any comments are welcome.

From an answer and comment, these are two alternative versions:

Alternative 1
This one moves the LED and the "pull down resistor" to before the NPN's base resistor and makes the microcontroller drive the LED itself. These are merely low power indicators, so 1-2mA is all that is needed, and with up to 6 of these on at any time, cannot afford too much output.
alternative 1

Alternative 2
This one uses the P FET's output to drive the LED this way, through a resistor for current limiting. This is coming from battery power, so can afford to be for more powerful and than if driving from the microcontroller output pins or my earlier attempt at piggybacking off the NPN transistor interface.
alternative 2

Best Answer

That LED being in the emitter - to - ground connection of Q3A is going to give you some grief since you've only got 3.3V (less actually because of the R7 R8 voltage divider on Q3A's base) to drive Q3A with.

Fix it by connecting Q3A emitter directly to ground, lose R8 and drive the base through R7, and connect the LED from the source of Q1 to ground through a suitable ballast resistor.

From your question:

"OUTPUT4 is the high power load output, which is connected to the Battery negative terminal through the system's common ground." might be better worded to indicate that one end of the load - not Q1's source - will be connected to battery minus.