Electronic – High-Speed PCB Design – Routing on Power Plane Layer

high speedlvdspcb-designsignal integrity

I am working on designing my first high-speed PCB with 4 layers (in order):

  • Top Layer: Single-ended/TTL signals
  • Internal Layer 1: Power Plane (3.3V)
  • Internal Layer 2: Ground Plane
  • Bottom Layer: LVDS signals

I have some critical connections made on the top layer but due to the layout of the PCB (which is pretty much fixed due to mechanical restrictions) I am unable to fit all of the single-ended signal traces on the top layer. Would there be a downside to moving some of these onto the second layer (containing the power plane), or should I leave the plane unbroken? The internal planes are intended to isolate the single-ended signals from the differential traces, and considering the ground plane (the plane closest to the LVDS traces) is still unbroken I was wondering if this could be done without causing signal integrity issues.

Best Answer

I assume all your high speed signals are LVDS.

If you are doing signal breakout from the top, then as long as you do not plough through with single ended signals in that area you should be fine.

If there is room on the bottom, that may be a preferable place (so you leave a solid plane). Just ensure you have decent separation rules.

That said, there is no general reason not to use a plane layer for a few single ended signals. Just make sure it is only a few so the copper balance in the stack is not out of whack. Your PCB vendor can help with this.

Give plane preference to the high speed signals, and assuming they are all on the bottom with a solid ground, you should not have any real difficulties as the LVDS signals will all be referenced to ground.