I'm interested in the history of the logic design for the edge-triggered D flip-flop, as used in the SN7474. The design is composed of three set-reset latches (six NAND gates total) per flip-flop.
Does anyone know what year the SN7474 was introduced, or have an early datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st Edition)? I've found it listed in distributor catalogs as far back as 1967 (year edited on 2017-07-21, previously I wrote 1971).
Another early datasheet I've found using this specific logic design for an edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The MC3060 is covered in the Motorola 1968 IC databook, on page 4-138. The 1976 TI TTL Data Book For Design Engineers 2nd Ed. lists the SN74H74 as direct replacement for the MC3060.
I've searched US patents for edge-triggered flip-flop design, but have not found one specifically for the three S-R latch design.
The subject came up as a result of a discussion on a private mailing list regarding the fact that the conventional J-K master-slave flip-flop design is NOT edge-triggered; pulses on J and/or K while the clock is high but stable can affect the Q (and not-Q) outputs of the FF at the following falling edge of the clock. That behavior is known as "pulse catching", and such a flip-flop is properly called pulse-triggered or level-triggered, but not edge-triggered. Early datasheets on J-K master-slave flip-flops actually had correct terminology and specifically stated that J and K should not change while the clock is high.
There are true edge-triggered J-K flip-flops which use a derivative of the three-S-R-latch D FF design, effectively generating an internal D input to the FF from J, K, and Q (and/or not-Q). The 74×109 is an example of that, using a not-K input rather than true K.
Master-slave D flip-flops effectively are edge triggered, unlike J-K master-slave. It is possible to build a true edge-triggered J-K master-slave flip-flop, by using a D master-slave with the internally generated D as described above.
CMOS edge-triggered flip-flop designs are almost always based on a master-slave design using transmission gates.
Best Answer
The Block II Apollo Guidance Computer (1965) used the three-SR edge-triggered flip flop circuit. I don't know if this was the origin of the circuit, but this pushes the date back a few years. The circuit is similar to the 7474's flip flop, but using NOR gates instead of NAND gates.
The AGC was one of the first IC-based computers, built out of NOR gates. It used S-R latches extensively; the edge-triggered flip flop is not as common but used for example here and here. A seven-gate variant is here.
(Thanks to Mike Stewart for info.)
Edit: I've come across a 1966 document calling this a "Westinghouse flip flop" (Apollo Block II and LEM Computer Design Review page E-1). American Microelectronics Data 1964-1965 shows the Westinghouse WM-2203 "six-gate binary counter" using this circuit. There's also a Westinghouse patent 3018388A for a flip flop that might be related. Finally, this NASA document from 1966 describes Westinghouse building a power supply synchronizer IC using this flip flop circuit, called a "six gate binary". I conclude that Westinghouse had a key role in the creation of this flip flop.