This circuit shows a clock generator, where a capacitor is charged to a certain voltage for half a period (phi opening switches S1 and S2). The same voltage but with negative polarity will be shown to the comparator input V_IN in the second half (phi bar) and slowly charged up back to ground. The comparator will create a clock signal if V_0 = 0 (shorted to ground), where the output is high in the first half and low in the second half.
From what I understand, the D flip flop will change the output at the rising edge of the clock signal generated at the output of the comparator with frequency f. Now here is the problem: isn't the output of the D flip flop going to have half the frequency (f/2) of its input? Doesn't this create a loop in which the output signal frequency (frequency of phi) is divided by two at every cycle?