I 'm looking for the best RC time constant and its reason in a PWM to convert digital signal to analog based on duty-cycle and frequency and other parameters. PWM frequency is 10 kHz.
Electronic – how determine the RC time constant in PWM digital to analog low-pass filter
analogdacpwm
Related Solutions
The simple answer is that you can't. There are several things going against you:
would be that for good audio quality you'd need to be very precise in your PWM generation. This is fairly difficult, as your master clock frequency (the freq that the logic used to generate the PWM from) would have to be around 100 MHz just to get the equivalent of an 11-Bit DAC. There are ways to generate PWM that good without that, but then you'd be starting with an analog signal and thus wouldn't have this problem.
as noted you would need a super steep rolloff of a filter. Just to match your 11-bit DAC equivalent you'd need something like 60 dB/octave-- which is unreasonable even for the pro's. There is a lot of difficultly in doing this kind of filter which is why everyone went to Delta-Sigma DAC's for their audio, which require about a 6 db/octave filter.
If your filter is not 60 db/octave then you'll need the PWM frequency to be super high. If you have 60 db/octave then you could have a PWM freq of 40KHz. At 54 db/octave then maybe 80 KHz will work. 48 db/octave = 160 KHz. Etc. Very quickly you get into the high MHz range-- and then your master clock frequency would have to be into the GHz.
All is not lost, however. Do you really need to filter out the high frequency stuff? In many applications (not all) you can either not filter it or use a simple RC filter at 1-5 MHz. There will still be high frequency stuff getting though but either the speaker or your ear will filter it all out. But the audio will still sound bad. AM Radio on a bad day quality. That's just the way it is.
Update: My numbers for #3, above, are somewhat wrong. But before I get to that, let me explain where I got all the numbers from.
Let's say that you are generating the PWM using digital logic (FPGA, Microcontroller, etc.). And then let's say that your audio sample rate and thus your PWM frequency is 48 KHz. And you want 8-bit resolution. That means that your master clock frequency should be 12.288 MHz. I calculated that this way: Master_Clk_Freq = Sample_Rate * 2^n_bits. Doing that again for an 11 bit resolution is 98.304 MHz.
The theoretical best noise level of an ideal DAC is about -6dB/Bit. So a 24-bit DAC has no better than -144 db noise. (Note: I'm playing a little loose with the terms here, lumping SNR, THD+N, and dynamic range all together.) Of course, no real 24-bit DAC can do this, but we're talking theoretical here. What this means is that an 11-bit DAC has about a -66 db noise level, so there is little point in making a filter that works better than this. AM Radio has approximately 60-ish dB signal to noise ratio, for comparison.
Ok, here's where I royally messed up the numbers. Assume that the PWM Rate = 48 KHz, and filter Cutoff=24 KHz (to make the math easy). With a -60dB/Oct filter we'll be -63dB @ 48KHz. If our filter were changed to -54dB/Oct then we'd be -57dB @ 48 KHz and -62.4dB @ 50.4KHz. What this means is that by changing our filter from -60db/oct -54db/oct we would have to change the PWM rate from 48 KHz to 50.4KHz to achieve the same filter blocking performance. Not a doubling of PWM frequency as I mentioned before. In the same way, if the filter were changed to -18dB/Oct (which is a manageable design) then the PWM frequency would have to be 104 KHz to still have -63dB filter attenuation at the PWM frequency. I calculated this by making a small spreadsheet and playing with the numbers.
Why figure 2 shows 0.7 of 1023 and cutting after ADC value of 700. Is it for opamp?
You almost certainly need to use a rail to rail (R2R) op-amp that is capable of producing a decent output close to the top power rail. If you are using something like an LM324, the soft clamping you see at the top of the waveform is likely due to it not being R2R on the high parts of the input signal and also on the high parts of the output signal.
Best Answer
The best RC is infinite, then you have a perfectly ripple-less DC output. Problem is that it also takes forever to respond to changes in the duty cycle. So it's always a tradeoff.
A first-order RC filter has a cutoff frequency of
\$ f_c = \dfrac{1}{2 \pi RC} \$
and a roll-off of 6 dB/octave = 20 dB/decade. The graph shows the frequency characteristic for a 0.1 Hz (blue), a 1 Hz (purple) and a 10 Hz (the other color) cutoff frequency.
So we can see that for the 0.1 Hz filter the 10 kHz fundamental of the PWM signal is suppressed by 100 dB, that's not bad; this will give very low ripple. But!
This graph shows the step response for the three cutoff frequencies. A change in duty cycle is a step in the DC level, and some shifts in the harmonics of the 10 kHz signal. The curve with the best 10 kHz suppression is the slowest to respond, the x-axis is seconds.
This graph shows the response of a 30 µs RC time (cutoff frequency 5 kHz) for a 50 % duty cycle 10 kHz signal. There's an enormous ripple, but it responds to the change from 0 % duty cycle in 2 periods, or 200 µs.
This one is a 300 µs RC time (cutoff frequency 500 Hz). Still some ripple, but going from 0 % to 50 % duty cycle takes about 10 periods, or 1 ms.
Further increasing RC to milliseconds will decrease ripple further and increase reaction time. It all depends on how much ripple you can afford and how fast you want the filter to react to duty cycle changes.
This web page calculates that for R = 16 kΩ and C = 1 µF we have a cutoff frequency of 10 Hz, a settling time to 90 % of 37 ms for a peak-to-peak ripple of 8 mV at 5 V maximum.
edit
You can improve your filter by going to higher orders:
The blue curve was or simple RC filter with a 20 dB/decade roll-off. A second order filter (purple) has a 40 dB/decade roll-off, so for the same cutoff frequency will have 120 dB suppression at 10 kHz instead of 60 dB. These graphs are pretty ideal and can be best attained with active filters, like a Sallen-Key.
Equations
Peak-to-peak ripple voltage for a first order RC filter as a function of PWM frequency and RC time constant:
\$ V_{ripple} = \dfrac{ e^{\dfrac{-d}{f_{PWM} RC}} \cdot (e^{\dfrac{1}{f_{PWM} RC}} - e^{\dfrac{d}{f_{PWM} RC}}) \cdot (1 - e^{\dfrac{d}{f_{PWM} RC}}) }{1 - e^{\dfrac{1}{f_{PWM} RC}}} \cdot V_+\$
E&OE. "d" is the duty cycle, 0..1. Ripple is the largest for d = 0.5.
Step response to 99 % of end value is 5 x RC.
Cutoff frequency for the Sallen-Key filter:
\$ f_c = \dfrac{1}{2 \pi \sqrt{R1 \text{ } R2 \text{ } C1 \text{ } C2}} \$
For a Butterworth filter (maximum flat): R1 =R2, C1 = C2