Electronic – How do we initialise unpacked arrays in Verilog

system-verilogverilog

Suppose I declare an unpacked array of size say 8 bits wide.

reg b[7:0];

If I want to assign b[7] = 1,b[6] = 1, b[5] = 1, ……b[0] = 1, then apart from assigning value to each bit is there a way to assign any combination of bits say 8'bA8, to b?

For instance if I execute this code(below) in verilog:

module tb();
    reg [7:0]a;
    reg b[7:0];
    initial begin
        $monitor("a = %b,b = ",a);
        a = 8'hA8;
        b = 8'hA8; // Line 7
    end
endmodule

I get this error:

C:\iverilog\bin>iverilog -o a test.v
test.v:7: error: Cannot assign to array b. Did you forget a word index?
1 error(s) during elaboration.

I am using Icarus Verilog on a command prompt on Windows 10 operating system.

Best Answer

Remember, b[7:0] means an array of eight 1-bit numbers. In your example you are trying to initialise it with a single 8-bit number, which is not the same thing.

For Verilog, you have to initialise each element in the array one by one:

b[0] = 1'b0;
b[1] = 1'b0;
b[2] = ...

You could also use a for-loop and localparam to initialise it, by storing the packed initialisation value in the localparam, then using the for-loop to copy it in to your unpacked array. As a bonus, the loop can be parameterised allowing you to change the size of the variable if you desire.

integer i;
localparam b_init = 8'hA8;
initial begin
    for (i = 0; i < 8; i = i + 1) begin
        b[i] = b_init[i];
    end
end

You could also try $readmemb or $readmemh if your synth tool supports it to load a binary or hex file of eight 1-bit numbers.

For SystemVerilog, you can do array initialisation:

reg b [7:0] = '{1'b1, 1'b0, 1'b1, ...};
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