Electronic – How does a “bulk connected to input voltage” mos work

The root of the problem to be solved by this circuit is that the Drain of the upper FET is not at a fixed voltage level (goes up & down), and you have to supply about 10V relative to its Drain at the Gate to open it.

What exactly the bootstrap capacitor is doing over here ?

It creates a voltage that is about (almost) V_CC + V_S. Since V_S is sometimes almost equal to the highest power supply line within the circuit (up to 500V or 600V, according to the drawing in the data sheet), there would be no way to get a voltage ~10V higher than that without some kind of "magic". The magic works by charging a capacitor through a diode to about Vcc when Vs is at GND (lower FET is conducting), and then this capacitor can provide the neccessary voltage level needed to open the Gate of the upper FET, and keep the Gate at a higher voltage even when the upper FET opens and V_S goes up.

Almost certainly it is because of the offset voltage of the LM324 which can be quite a few millivolts in either direction.

It would act as if you have a few millivolts at the input even when there isn't.

If for example the opamp has 7mV offset it will drive the MOSFET to produce 7mV across Rs - about 1.5mA with a 4.7 ohm sense resistor. If the offset had been the opposite polarity then it would have turned off the MOSFET altogether.

Changing the threshold of the MOSFET won't help as it is inside the negative feedback loop and the opamp will just change its output to keep the commanded current flowing through Rs.

One way to avoid the problem is to force a small current through Rs even when the MOSFET is off. You need at least 1.5mA (the current caused by the worst case offset) - this would require a 5.6K resistor from the source of the MOSFET to the positive terminal of the power supply (assuming an 8.5V supply). This will guarantee that the MOSFET will be off even with up to 7mV of offset in the opamp.

Also that circuit as designed may be unstable as the 10K resistor you have feeding the MOSFET gate is rather high - it will interact with the input capacitance of the MOSFET and give a delay in the negative feedback loop (also called a Pole). I would change Rg to 100 ohm. From your opening sentence I gather the schematic is not correct but bear this in mind if you do use a resistor feeding the gate.

Edit - corrected the calculations for 7mV offset and 4.7 ohm sense resistor as pointed out by Andy Aka.