Electronic – How does CLKOUT works on the LTC2323-12 ADC on “High-speed” speed mode

adcfpgatimingverilog

http://www.farnell.com/datasheets/1833817.pdf

I was assigned a task where I have to connect an LTC2323-12 ADC (analogic to digital converter) to an FPGA.

Reading the LTC2323-12 datasheet seemingly it has two ways to be controlled. One way is through the SCK (clock-like) input that cycle by cycle shift the ADC results out of the ADC to SDO port.

The other way is described as a "high speed" that can "ease the timming requirements for the FPGA" (would you clarify this for me?) , this last one method is trough the CLKOUT signal, which is seemingly a Clock that comes out of the ADC that is matching (or latching) the ADC results out of the SDO port. Is that correct? Did I get it correctly?

So do I have to design the FPGA module in order to output the CNV signal of startup, then keep it for TCNVH nanoseconds, then release it, then just wait until ADC AUTOMATICALY send the first CLKOUT, so I can register it and count 11 more of these CLKOUT, while passing the SDO data out to my own registers on each of these CLKOUT cycles?

Then after the last 14 CLKOUT clocks, I must design a counter that trigger a valid signal that will start another counter of TDSCKLCNVH nano seconds, and at the same time porting out of this register register and a "Finishing" signal (so another top module with the same clock than my fpga module, can make use of these signals in another moment.

I would like you to correct me if I misunderstood something about the behavior of the LTC2323-12 ADC and the way to approach it. Thanks in advance.

Best Answer

The other way is described as a "high speed" that can "ease the timming requirements for the FPGA" (would you clarify this for me?) , this last one method is trough the CLKOUT signal, which is seemingly a Clock that comes out of the ADC that is matching (or latching) the ADC results out of the SDO port. Is that correct? Did I get it correctly?

Yes, that is correct. Your data receiver can use CLKOUT to latch the data coming from the ADC. The CLKOUT signal and the data out can be delayed by PCB tracks feeding the FPGA (receiver) and if both are created at the ADC and generally routed along similar paths to the FPGA then they will remain in sync no matter whether it's millimetres or several centimetres between ADC and FPGA.

The SCK line comes from your FPGA and if it was used to latch in your digital data then there is a clock delay going to the ADC and a delay to the data coming back and this can mean (on longer PCB tracks) that you won't latch clean data.

So do I have to design the FPGA module in order to output the CNV signal of startup, then keep it for TCNVH nanoseconds, then release it, then just wait until ADC AUTOMATICALY send the first CLKOUT, so I can register it and count 11 more of these CLKOUT, while passing the SDO data out to my own registers on each of these CLKOUT cycles?

Yes, to get optimum high speed performance on longer PCB tracks.

Then after the last 14 CLKOUT clocks, I must design a counter that trigger a valid signal that will start another counter of TDSCKLCNVH nano seconds

Yes, according to the timing diagram above (which I've also added a few minimum timings to).

Related Solutions

Electronic – Unexpected Verilog warning re FPGA clock assignment

The warning is basically suggesting that you use an explicit clock primitive, which for whatever reason isn't inferred automatically by the tools.

There should be a reference for your particular FPGA that tells what primitives are available. For a Spartan3E, for example, Xilinx UG617 describes the BUFGCE primitive ("Global Clock Buffer with Clock Enable") and shows how to instantiate it. Other vendors will have similar documentation.

Your clock distortion is probably occurring because tristating an output line isn't something that can be done instantly. Whatever is being driven has both inductance and capacitance, so even if the driver could go high-Z in zero real time (which it can't), the driven network will continue to ring for some time. If that's a problem, you would need to find a way to ensure that the clock line is low, and has been for some time, before tristating it. All in all, there is probably a better way to accomplish your goal besides tristating a clock.

Electronic – Generating Channel Select for Multichannel ADC

It looks like you're trying to make logic with an asyncronous reset signal called cs.

But you mismatched the edge sensitivity for the reset signal. You're watching for the falling edge of cs, but the logic calls for resetting when cs is high.

You need to either have sensitivity to posedge cs and reset the registers when cs is high, or have sensitivity to negedge cs (like you have) and reset the registers when cs is low.

For example,

always @(posedge clk or negedge cs) begin
    if(~cs) begin
         count <= 0
         ...
    end else begin
         ...
    end
 end

Best Answer

Related Solutions

Electronic – Unexpected Verilog warning re FPGA clock assignment

Electronic – Generating Channel Select for Multichannel ADC

Related Topic