So I have really been hitting the example code hard this week in an attempt to better understand some HDL design basics, specifically FPGAs with VHDL. The book I am using (if anyone is interested) is "FPGA PROTOTYPING BY VHDL EXAMPLES" by Pong P. Chu.
After a few examples, I am starting to wonder.
How does someone initially design a digital system for HDL?
(Flowchart/Block diagram? Signal list? etc)
For example, I love to use Logisim to flesh out simple digital circuits. The graphical interface is easy to follow and I can get on-the-fly simulations without all the synthesis. But when I am satisfied with my Logisim design, I find it difficult to transfer that design into HDL.
Is there a way to understand how you should structure your HDL design, or does it just come with practice?
Best Answer
I generally take a top-down design approach, and I start by drawing a block diagram that shows the interfaces among the top-level blocks. I then draw additional diagrams that represent the implementations of the top-level blocks in terms of lower-level blocks.
This hierarchy of block diagrams translates pretty much directly to the hierarchy of the HDL modules. Once I get to a low enough level of detail on the block diagrams, I start coding and stop drawing diagrams.
The block diagrams also function as dataflow diagrams, since they show at every stage how the data flows from one module to another.
When it comes to specific interfaces between modules, I also draw timing diagrams that show the details of the interface protocol. I also use timing diagrams to keep track of the flow of data through the pipeline stages inside a module. In both cases, these diagrams serve as a reference when looking at waveforms in the simulator during verification.