To answer your base question, to get to the address of pin A10 of the memory you need to look at the memory map for the ARM device...
In this case it looking at the memory map:
0x8000 0000 -> 0x8FFF FFFF is mapped to CSD0 (SDRAM/DDR)
and
0x9000 0000 -> 0x9FFF FFFF is mapped to CSD1 (SDRAM/DDR)
You'd need to know what chip select was used in the PCB design to determine your answer as to which bank your DDR is attached to.
This implies that A10 is located as either 0x8000 0400 (as you mentioned) or 0x9000 0400.
As to why 0x8000 0F00 was used in place of 0x8000 0400...reading the datasheet for that memory implies, but does not state that the other address pins, A(n) are don't cares for this operation so the coder probably just tossed in an F there instead of figuring out that it was only a 4 that was needed.
I also don't find those 2 sections of the datasheet to contradict each other. The first is basically just saying that you need to reference the device's memory map to locate the real address where the memory is mapped so you can use that address as a base.
The second quotes tells you that bit 0 of the address corresponds to address pin 0 on the memory in this mode, which may not always be the case in normal operation. It may depend on the data/address width of the memory combined with alignment issues for the core.
Best Answer
You have a couple of options.
You can add the extra hardware in the data path to allow it to occur in one cycle. This has difficulties in a pipelining architecture because a dual port register file is often used for simultaneous reads and writes for the different stages. This adds the need for a second write port. Without this, there really is not a way to prevent a bubble in the pipeline from eventually having to occur.
A generally better option is to simply have a multicycle instruction. The important thing here is to make sure you prevent any other operation such as interrupts or other bus masters (in the case of a memory swap) from make this appear non-atomic.
The multicycle instruction option is what is generally done. For example, the ARM SWP and the XCHG instructions are multicycle.