Electronic – How instruction skipping is avoided during procedure calls in pipelined architectures

cpu

I have a question regarding a PC register (IP in x86 lingo). In most architectures it is updated during an execution stage and thus stores an address of a next instruction to be fetched. It seemed clear to me until I started to reason about a pipelined architecture. For example, imagine the following classic RISC pipeline with 5 stages (Fetch, Decode, Execute, Memory access, Write back) which is filled with the following instructions (designated as "a", "b", "c", "d"):

F D E M W
c b a - -

0x12 call [0x100] ; a
0x14 mov ax, 10   ; b
0x16 add ax, 2    ; c
0x18 nop          ; d <- IP

By the time an instruction "a" reaches the E (Execute) stage in the pipeline, it is already full with subsequent instructions and IP points to an instruction at address 0x18 (the next one to fetch). When "call [0x100]" executes, it saves the contents of the IP (a return address) on the stack. But it's obviously not the address of the instruction following "call [0x100]"! So, as we return from the CALL, we effectively jump over 2 instructions since pipeline is flushed during the CALL execution!

Which means that:

  • There is another hidden register storing the address of the instructions being executed and it's stored on the stack instead of IP
  • It doesn't work this way
  • I am missing something 🙂

Best Answer

Reading through the reference manual on the X86 assembly... https://courses.cs.washington.edu/courses/cse548/05wi/files/x86-reference-long.pdf

you will find this... "The call instruction calls near procedures using a full pointer. call causes the procedure named in the operand to be executed. When the called procedure completes, execution flow resumes at the instruction following the call instruction (see the return instruction)"

This tells you that the call has to return first. This means that when run, noop instructions will be placed after it until it returns.

Immediately after this is called, the Control block will determine it is a call, which is a command requiring action by the hazard detection unit. This unit fires off what is essentially a call interrupt. So immediately upon seeing this instruction this interrupt occurs to call noops and will not allow PC to increment.