According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following:
The single-cycle microarchitecture executes an entire instruction in one cycle. (…)
The multicycle microarchitecture executes instructions in a series of shorter cycles. (…)
The pipelined microarchitecture applies pipelining to the single-cycle microarchitecture.
Architectures are often classified as either RISC or CISC. From RISC vs. CISC:
RISC processors only use simple instructions that can be executed within one clock cycle.
Since MIPS is RISC architecture, I am a litte confused by the above definitions and wonder if there isn't some sort of contradiction between them. More specifically:
- If a RISC instruction can be split into shorter cycles (Fetch, Decode, …), how can we say that it only takes one clock cycle to execute the whole instruction? Doesn't it take one clock cycle to execute each of the steps?
- Does it really take one clock cycle to execute one RISC instruction? What happens, for example, if a cache miss occurs and the processor has to wait for slow DRAM? Shouldn't this prolong the execution of the instruction by quite a bit?
- What exactly is one instruction cycle? Is it the time that it takes for one instruction to finish (i.e. one/multiple clock cycles)?
- How long does one CISC instruction take in clock/instruction cycles?
Best Answer
The practical definitions of RISC and CISC are so muddied and blurred now they are almost meaningless. Now it is best to think of them as more about "philosophy", in the sense that a CISC architecture has a richer instruction set with more powerful individual instructions (e.g. DIV and the like) while a RISC instruction set is bare bones and fast, and leaves it to the compiler to implement complex operations. Even purportedly CISC instruction sets (like x86) are translated into internal instructions in both Intel and AMD chips and implemented more like RISC processors. To answer your questions:
The original academic RISC processors (and I think maybe the very first commercial versions) did indeed execute one instruction per cycle, including fetch and decode. This was possible because the datapaths were super clean because the operations of each stage were simple and well defined. (the tradeoff here is only very simple instructions can be implemented this way). Once it hit the real world things got blurred. Things like pipelining and superscalar architecture make a simple RISC/CISC dichotomy impossible.
The original RISC chips attempted to execute one instruction per cycle and they could if the data was available in the register file. Of course if the processor had to go to DRAM it would take a (lot) longer. RISC is about "attempting" to execute an instruction per cycle.
One instruction cycle is the time it takes between fetches.
In depends enormously on the instruction and the instruction set architecture. Even in a CISC architecture some instructions could execute very quickly (like a shift left or right for example). Some executed very slowly (10s of cycles or more). The VAX architecture (probably the pinnacle of the CISC philosophy) had instructions that were really complex. Incidentally, a CISC architecture is usually easier to program in assembly than a RISC architecture because it is almost like a high-level language!