All memory cells have their level, either 0 or 1. The CPU tells the memory device which cells it needs the binary values of, and supplies this address to the memory device. Inside the memory device the address is decoded in a row and column address, and the cell at that position in the matrix is allowed to gets its data to the databus, i.e. the data pin.
Let's say we have an 8-bit address 01100101. This will be split up in a row address 0110 (the high order nibble) and a column address 0101 (the low order nibble). The row address selects row #06, so all cells connected to this row will have their data ready. The column address selects the cell at column #05 of this row, so that finally only one single cell is allowed to place its data to the output pin.
Storing data follows the same pattern: only one row is selected, and the cell at the given column in that row will get the data present on the pin stored.
This is for 1 bit. The operation occurs for the full data word width simultaneously, so if you have a byte-wide memory, 8 bits are retrieved and their value placed on 8 databus pins.
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This picture should help you seeing things better:
This is a representation of a DRAM array, where data is stored in the charge of the capacitors, each capacitor is one bit. The row part of the address (here A1..A0) selects a row, which means they activate all FETs on that row, so that the levels of the capacitors for that row become available on their corresponding column. Then the column address selection block, controlled by the other part of the address, A3..A2, selects the one bit which we want the data from.
DRAM is easy to build, but has a nasty disadvantage: reading the data discharges the capacitor, so the data is lost. To counter this DRAM has sense amplifiers, which detect the current memory cell status and refresh it when read. In addition this refresh has to be done periodically because the capacitors' charge will leak away even when the memory isn't read. The need for refresh circuitry is easily compensated for thanks to the DRAM's cells' compactness.
SRAM uses a couple of transistors to store the data, and it isn't volatile in the way DRAM is (though the data is still gone when you switch the power off). With EEPROM and Flash the data is stored in the (insulated) floating gate of a FET, and therefore it won't lose its data when power is switched off.
Further reading:
This answer about data retention in Flash memory.
Cycle as used on that web page means "clock cycle": the time taken for one pulse of the clock signal used by the ram. So the 100MHz clock corresponds to a 10ns cycle.
Internally, this corresponds to selecting a row within the chip and reading the corresponding column lines; this brings out a set of values (let's say 256 bits = 8 bytes), for each of the 8 chips on the RAM.
There then follows a response burst where the values are transferred back to the processor. The bus is 64 bits wide, so there will be several transfers. Usually this fills an entire cache "line".
(Note that there is an implicit pipeline: you can send out another request before the first has finshed)
For an FPGA project, you'd use onboard SRAM in preference, but if there isn't enough or you need to share it, you would use external DDR RAM.
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Don't forget about VTT termination power. Also they have some excel power calculators: micron.com/products/support/power-calc A quick look at their calc showed standby power was around 100mW. The calc seems to have really good info.
Re: VTT Term I believe you're correct when you're not doing anything the power consumed is probably negligible. In DDR you need to provide VTT termination for the signals, basically a resistor tied to 1/2 your VDD voltage. Again it probably doesn't mean anything for power.
Don't forget that you have to refresh the DDR periodically, setting it into self refresh mode should do that for you. That should be your lowest power mode, and you don't have to provide a clock to it at that point.
Oh and if you can, consider LPDDR, the lower power stuff is around 1.35V now I think. I just read an article the other day that low power dram orders have now surpassed regular DDR so it might even be cheaper for you.