Electronic – How SPI and I2C latch data

i2cintegrated-circuitinterfacespi

I got questions about the working mechanism and measurement method of SPI and I2C interface.
For SPI, there are several modes.
My question is, how will the data be latched?
Take CPOL=1 and CPHA=0 for example, the bit is latched at the falling edge of clock.
But, why is it the same for MISO and MOSI?
I mean, MISO and MOSI come from different devices(the former from device and the later from master).
But the clock always come from master.
So how would it possible to latch both MOSI and MISO by the falling edge of clock?
For MOSI maybe yes, since the clock and the MOSI output together from master, and arrive device at the same time
(maybe I should say half clock later).
So it's possible for MOSI to follow the timing diagram.
But for MISO, how do we let the MISO be latched at the center of its bit, since it'll travel an uncertain flight time from device to master?
And for scope measurement, which point should we probe? MOSI on device side and MISO on master side?

I got the same question on I2C.
How to make sure the SDA data will be kept high when it's from master to slave, and from slave to master, since the clock is
always from master to slave?

Thanks for any feedback! 🙂
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Best Answer

So how would it possible to latch both MOSI and MISO by the falling edge of clock?

The diagram are meant for illustration purpose only not a detailed one inside the chip, let us assume the data is capture on falling edge, assume the slave is transmitting data, now on the falling edge of the clock, the slave output the bit (say MSB on first clock), the output will be held by the slave till rising edge of the CLK input, master can allow the slave data till the rising edge of the CLK and then shift the bit right, the same repeat till all data bits are received, the same apply to MOSI from master.

Another, explanation using SS (slave Select also called Frame Synchronization I/O Pulse), when SS bit goes low (see the picture) the slave out put the data, on falling edge the data is captured which is approximately center of the data pulse on rising edge next data is shifted to the output, so we have CLK pulse width time for data to settle in the output pins and master to capture the data from slave

SPI peripheral module will have all necessary timing, shifting circuit to make it functional on worst case situation.