I'm building a system in Quartus according to this question
How to upgrade a Quartus II project from SOPC to QSys?
Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus I don't have the options.
Can you help me?
Update
The suggested changes did not work for me as Quartus displays error messages that I can't interpret:
Update 18:07 130828
Now I only have 1 error left in the component editor:
Error: reset_sink: Synchronous edges DEASSERT requires associated clock
What does it mean?
Best Answer
You need to add clock and reset signals to the source code (VHDL) for this block. Then refresh the ports list in Component Editor and set the Interface type to be Clock Sink and Reset Sink for those signals. It looks like SOPC Builder would let you design a totally combinatorial block and ignore the warnings about no clock specified on the Avalon-MM interface, QSYS requires it.
Then configure as follows: