Electronic – How to avoid a clock glitch


I have a clock with a 50% duty cycle, driving a 3-bit ripple counter.

When Q2 is high, external lines such as address are stable. I want to generate a short read pulse between 50% and 75% of the Q2 signal to latch in data from external RAM / ROM.

Below is what I am using in LogiSim. But if I remember back to my digital electronics days (1980!), I can get a glitch between when the counter (Q2, Q1, and Q0) changes state, which might trigger a spurious RdPulse.

Is there a race hazard (e.g., when the counter changes from 111 to 000)? And if so, how can I avoid it?

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Best Answer

To avoid the possibility of the glitch, you might consider making the read signal a registered output. This will require some redesign of your state machine, since if you simply put a register in front of your AND gate, the read pulse will occur almost one clock cycle later than without the register. Therefore you will have to change the fan-in to your AND gate to select state 101 rather than what you currently have, which selects state 110. With this done, you may put a register in front of the AND gate clocked from the same clock as the counter. This will generate the read pulse at about the same time in the 8 state cycle as what you currently have but without the possibility of the glitch.