Like endolith says you have to look at the conditions for parameters. the 30nC are a maximum value for \$V_{GS}\$ = 10V. The graph on page 3 of the datasheet says typically 10nC @ 5V, then C = \$\frac{10nC}{5V}\$ = 2nF. Another graph also on page 3 gives a value of 1nF for \$C_{ISS}\$. The discrepancy is because capacitance isn't constant (that's why they give a charge value).
The gate resistance will indeed have an influence. The gate's time constant will be (9\$\Omega\$ + 3.6\$\Omega\$) \$\times\$ 2nF = 25ns, instead of 9\$\Omega \times\$ 2nF = 18ns.
In theory there will be a slight difference between switching on and off, because when switching off you start from a higher temperature. But if the time between on and off is small (lots of margin here, we talk about tens of seconds) temperature is constant, and the characteristic will be more or less symmetrical.
About your side question. This isn't usually given in datasheets, because the current will depend on \$V_{GS}\$, \$V_{DS}\$ and temperature, and 4-dimensional graphs don't work well in two dimensions. The only solution is to measure it. One way is to record \$I_D\$ and \$V_{DS}\$ graphs between off and on and, multiply both and integrate. This transition normally will happen fast, so you'll probably can measure only over a few points, but that should give you a good approximation. Doing the transition more slowly will yield more points, but the temperature will be different, and hence the result will be less accurate.
Some of the things you say are conflicting, so I want to be clear about the question I am answering. If this is not the question you intended, then you need to write a better question.
The question is what is the voltage accross C1 over time when it initially starts at 0. You didn't specify a capacitance, so we'll leave that as the variable C.
There are two separate regimes to the C1 voltage over time. The first is when the supply is in current limit mode. In that case, the capacitor is being charged up linearly. When the capacitor reaches 9 V, the supply switches over to constant voltage operation. After that, there is a exponential decay from 9 V to 10 V governed by the RC time constant.
The voltage rise of a capacitor is dV = I dT / C. We know the current (I) is 1 Amp and that dV will be 9 V in the first part of the function. The time to reach 9 V is dT = dV C / I. For example, if C = 470 µF, then the time to charge from 0 to 9 V is 4.2 ms. The capacitor voltage will rise linearly during that time.
From 9V on, the supply will be at a constant voltage of 10 V. This remaining 1 V rise will occur as a exponential according to the time constant RC. Again using 470 µF as example for C, that time constant would be 470 µs. That means, for example, that 470 µs after the capacitor has reached 9 V, it will have gained another 630 mV, which would put it at 9.63 V in absolute terms.
Added to clarify why the crossover point is 9 V:
Work backwards and assume the supply is always putting out 10 V. At what capacitor voltage does that require 1 A or more? Since R1 is 1 Ω, 1 A thru it causes a 1 V drop. If the supply is 10 V and R1 drops 1 V, then there must be 9 V on the capacitor when the current is 1 A. If the capacitor voltage is lower, then the voltage on R1 must be higher, which means the supply has to source more than 1 A. However, we know the supply puts out the lesser of 10 V or 1 A, so delivering more than 1 A is not possible. This means for capacitor voltages below 9 V, the supply voltage will be the capacitor voltage plus 1 V, since 1 V will be accross R1 when the supply is putting out 1 A.
Best Answer
The step by step time constants
I coloured zones for dynamic losses.
When using a driver with matched impedance to the gate resistance, Rg ;
As once written, seek and ye shall find. or re-Search, next time DIY.
From your datasheet...
spec: VGS = 4.5V, RGEN = 6 Ω You are driving gate with 1k5 instead of 6 Ω , so we use total Gate Charge equation and datasheet specs instead using worst case.
So effectively with a high source R you are driving with a current source Ig=Vgs/R then from $$ I_g = ΔQ_g/Δt_s , (ΔQ=Q) , Δt_s = Q_g/I_g = Q_gR_g/V_{gs} = 5nC_{max}\cdot 1k5/5V=1us$$
Yet if we simply used T=RC=1k5*195pf=293ns (typ) (0.3us) is only 30% typ of the more accurate worst case gate charge times.
The Miller plateau for a current source gate drive means that from C=Q/V is Vgs is flat and Q jumps to the right, that means C rises until Vds drops to minimum. This is a negative feedback effect.