Electronic – How to calculate resistor values for a VGA DAC

dacvgavoltage divider

I have an FPGA and want it to drive a VGA monitor. I want more than 3 bits of color so I need a DAC of some sort. So I want to make a resistor dac.
My plan is to have 3 bits per subcolor. So total of 9 bits per pixel. I know VGA monitors have an impedance of 75 ohm that I need to take into account, and I know they need 0 for black, and 0.7v for white.(per subpixel)

Problem is I don't know how to continue with this info, I believe I need to use algebra for this, but I'm still learning that and therefore have some issues calculating the correct resistor values.

So first I think I need to figure out what resistor value I need to get 0.7 v taking into account the 75 ohm to ground. Which wounds like a resistor divider to me, if I'm correct, when I use 3.3v as input, I'd need a 280 ohm resistor to approximately get 0.7v.(I used the formula on the wikipedia page for resistor dividers)
But I don't know how to continue from here.
How do I know what 3 resistor values I need that would give me the correct voltages?(Also, bit 2 needs to give more voltage than bit 0)

Can anyone help me with that? And also explain what you are doing to get me the values so I can learn it too?

In case I do need to use algebra, I only know the basics like solving 3x+3=2x+7 so a little help there would be appreciated.

Thanks!

Best Answer

The simplest thing to do is to build a 3-bit "R-2R" DAC for each channel, using 75Ω resistors. The cool thing about this kind of DAC is that its output impedance is simply "R", which means that you can connect it directly to 75Ω coax with no termination issues.


If you build a 4-bit DAC, but tie the MSB to ground, you'll get close to the voltage range you need:

schematic

simulate this circuit – Schematic created using CircuitLab

The Thevenin source voltage is reduced by the voltage divider created by the Thevenin source resistance and the monitor termination resistance, resulting in a range of 0.00V to 0.72V on the line.

The worst-case load on any of the FPGA outputs is approximately 3.3V / 225 Ω = 15 mA.