Electronic – How to check if a comparator is broken

This doesn't answer your question about the low gate voltage, but I want to explain the hysteresis I suggested in comment you might add.

Suppose the diode ladder creates a voltage difference of 10V, then the inverting comparator input is at 6.5V. Also let's start with the situation where the capacitor is fully charged to 16.5V, then the non-inverting input is at 0V. So output is low, FET doesn't conduct, and C1 is allowed to discharge through its load. When the voltage across C1 becomes 9.99V the non-inverting comparator input becomes 6.51V and the FET starts to conduct, so that C1 gets charged. This means \$V_{OUT}\$ will start to decrease, falling below 6.5V again and the FET will switch off again. Charging will stop, and C1 will again discharge until it reaches 6.51V again. Same things happen: FET switches on, \$V_{OUT}\$ will descrease and FET will switch off again. And so on.

That's the theory. I made my comment before I had seen your schematic, based on the description. Now since you charge C1 over a very low resistance its voltage may go pretty low before the FET switches off again, but things may also occur as described above.

What can you do about it? This is where the hysteresis comes in. Like I said you add part of the comparator's output voltage to the non-inverting input. Place a resistor between \$V_{OUT}\$ and the non-inverting input, and one between the output and the input. Now if the FET is off the output is low, and the resistors will form a divider, so that the non-inverting input sees only part of \$V_{OUT}\$. That's your comparison level. You'll have to adjust the reference voltage on the other input. Say that you're now comparing with +5V. OK, C1 discharges until it reaches 5.01V. Output becomes high and C1 starts to charge. Now this is important, via the resistor divider the high output will set the non-inverting input to a level much higher than the 5.01V. This means that the output will remain active for a longer time (C1 voltage has to charge all the way down to 5V). This will ensure that C1 gets fully charged via the FET's internal resistance, before the FET gets shut off again.

U1b can be disabled from oscillating by dragging pin 5 to +5V or by dragging pn 4 to ground. I favour taking pin 4 to ground because then the 70ohm load is not being powered at all when disabled.

To do this I would connect the output from U1a via (say 1k) to pin 4 of U1b. Because it is an open collector output it will do nothing when not active so get rid of R3 to ensure this.

Now this may mean that the pot on U1a operates in reverse but that can be fixed by swapping the circuits on the input pins of U1a.

If there is an unforseen impedance on the inactive output of U1a that disturbs the oscillations of U1b then maybe a diode connection to U1b is better (cathode to U1a o/p)