I'm late to the game, but I'll give it a shot:
1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?
Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.
2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?
Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.
3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?
Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.
4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.
The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.
Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).
5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?
It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).
Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.
Best Answer
There are two values you need to worry about: voltage drop, and power dissipation. Both are simple Ohm's Law and are functions of the trace resistance.
The trace resistance is a product of its cross sectional area, and its length.
Reduce the length and you reduce the resistance. Reduce the width and you increase the resistance.
So you can have a shorter run of a narrower trace and still handle the current.
The formula for calculating the resistance of a trace is:
$$ R = \rho \frac{l}{A} \cdot (1 + (\alpha \cdot \Delta T)) $$
So for a 300 thou (7.62mm) trace at 1oz, which is a thickness of 0.0347mm, a rectangular cross-section would be
$$ 0.00762 \times 0.0000347 = 0.000000264m² $$
Of course, with etching and other factors it won't be as thick, nor perfectly rectangular, so reduce that a little - let's say for the sake of convenience it's 0.0000002m².
Then you have a trace that's 0.05m long (5cm). What is the resistance of that trace at, say 23°C?
$$ R = 1.68×10^{-8}\frac{0.05}{0.0000002} \cdot (1 + (0.003862 \times 3)) $$ $$ R = 1.68×10^{-8} \times 250000 \times 1.011586 $$ $$ R = 0.00425\Omega $$
So once you have the resistance, and you know the current, you can apply simple Ohm's Law to it. Say 15A, your upper value.
The voltage dropped across that trace is $$ V=IR = 15 \times 0.00425 = 0.064V $$
The power dissipation will be $$ P=I^2R = 15 \times 15 \times 0.00425 = 0.956W $$
So now you can calculate what the voltage drop and power dissipation would be over your small traces to see if it's tolerable.
There are also various tricks you can employ for handling larger currents. One of the most common (and old-school) is to leave the traces unmasked, then flood them with extra solder. This massively increases the cross-sectional area thus reducing the resistance. You can also use electro-plating to achieve a similar result, though this is considerably harder to do, especially in just a small area of the board.
Using wires instead of (or as well as) traces can also be done.
As an aside, you should also consider if the connections, and the pins used in your connectors, are suitable for carrying up to 15A.