The interface to an AC97 codec is a bit more complicated than straight digital audio. The serial data consists of 256-bit data frames; each frame contains several channels of 20-bit samples. The overall data rate is 12.288 MHz; dividing by 256 gives the sample rate of 48 kHz. Part of the 256-bit frame is dedicated to control messages, e.g. to set mixer registers. You may need to do this once after power up/reset to set the volume.
The AC97 spec is available from Intel. Writing your own master is not unreasonable but it will take some time. You may also be able to find one you can reuse. OpenCores has one. There's a very barebones AC97 controller and some general information about the protocol here.
I can't remember how many of the AC97 registers are standardized. The manual I found online for your board says it has an LM4550 codec. Assuming that's right, you may want to refer to the LM4550 datasheet for a complete list of configuration registers.
Have you simulated the code to make sure it does behave OK in the ideal world?
Also, 100MHz is quite a fast clock and unless you tell the tools that's how fast you want to go, you might find it doesn't work. The logfiles should report what the final timing numbers are. You don't need to use a DCM, but if you want to, in the libraries guide there is a sample VHDL instantiation template, or you can use CoreGen.
As others have said, it's conventional to use the rst
signal to reset your design, especially your counter. With FPGAs you can get them to startup in a known state. but it's often easier (especially to get it to match with simulation) to have an explicit reset. When you do this, check the polarity of the reset signal - sometimes they are active-high and sometimes active-low.
If you are using XST for synthesis, it should work fine with initial values. And even if it doesn't, the blink
inversion will work, it'll just start from '0' not '1'. And the counter will start from all-zeros.
So:
- Simulate the design, make sure it toggles in simulation first.
- Add a PERIOD constraint to the UCF file to put a 10ns constraint on the clk signal.
- Also, check the
.pad
file to see that the things you think you have constrained to the pins actually have gone on the right pins.
Best Answer
There is a set of Linux drivers by Michael Gernoth to replace the ones provided by Xilinx. I used them with a parallel cable, but they are designed for USB cables originally (though the Digilent USB cables are not in the list, but it might be worth a try).
I also needed to run ISE as root, and to preload the proper libraries. I did a writeup of my experiences, since there were also some other issues.