Electronic – How to double the clock’s frequency using digital design


I am trying to double my clock's frequency using only gates, flip flops or whatever but unfortunately I get a signal of which the duty cycle is far from 50%. Unfortunately I have to develop my system using FPGA but the chip I work with, does not support a PLL so before trying to work with another board I want to be sure that I cannot get the double frequency of my input clock. The input frequency of my system is 10 MHz and I want to make a signal of 20 MHz. I have done it using the attached circuit and I have also measured it but the duty cycle of it is not satisfying at all. Please I would appreciate if could someone suggest something that could be helpful.

Here is the circuit I have used.


Best Answer

A PLL is generally required to achieve what you want to do. Trying to use just logic to do this requires the addition of some extra delays via R/C time constants to bring the 2x pulses up to near 50% duty cycle. However that will not generally happen inside an FPGA without bringing some signals to pins on the part where the R/C can be connected and then fed back into other pins. Another limitation is that such scheme will not be right on 50% duty cycle and for a given set of R/C values will only be useful at a particular narrow range of input frequency.