I want to create a schematic of a specific verilog module hierarchy showing which blocks are connected to which other blocks. Much like Novas'/Springsoft's Debussy/Verdi nschema tool, or any of a number of EDA tools that provide a graphical design browser for your RTL.
What tools area available to draw schematics programmatically either from a verilog or vhdl definition, or from some other text-based input format?
Best Answer
Use Yosys, the free and open source awesomeness HDL Synthesis Toolbox with extra doses of being cool (and free) (and faster than current-gen Vivado) (did I mention Free as in speech & beer?) (and awesome)!
Get yosys, and the xdot utility (often part of a package called python-xdot) as well as graphviz.
Then, do something like in a verilog file (let's call that
minifsm.v
):and run yosys:
load the verilog file, then check the hierarchy, then extract the processes, optimize, find the state machines, optimize, and show a graph:
and you'll get something like
With different options to the
show
command you can also just save the graph to a file. Yosys allows you to write "flattened" logic in verilog, EDIF, BLIF, …, synthesize and map for specific technological platforms, including these supported by ArachnePnR, and do much more interesting things. In essence, Yosys is like letting someone who knows how to build compilers write a verilog synthesizer.